Structure with self-aligned offset gate contact and direct backside contact
A semiconductor structure is provided that includes a self-aligned offset frontside gate contact structure and a direct backside source/drain contact structure. The presence of the off-centered frontside gate contact structure is attractive since it mitigates the risk of gate contact-to-source/drain contact shorts and it also improves the metal line, M1, spacing within the overlying frontside back-end-of-the-line (BEOL) structure.
1 . A semiconductor structure comprising:
a transistor comprising a gate structure, a first source/drain region present on a first side of the gate structure and a second source/drain region present on a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure;
a gate spacer located on the first side of the gate structure and a recessed gate spacer located on the second side of the gate structure, wherein the recessed gate spacer has a height that is less than the gate spacer;
a dielectric cap located on a first surface of the second source/drain region;
an off-centered frontside gate contact structure having a first portion located directly above, and in direct physical contact with, the gate structure of the transistor, and a second portion off-set relative to the gate structure and located directly on the dielectric cap; and
a backside source/drain contact structure located on a second surface of the second source/drain region, wherein the second surface of the second source/drain region is opposite the first surface of the second source/drain region.
2 . The semiconductor structure of claim 1 , further comprising a gate cap pillar located adjacent to the off-centered frontside gate contact structure and on the gate structure.
3 . The semiconductor structure of claim 2 , wherein the gate cap pillar is located on a first side of the first portion of the off-centered frontside gate contact structure and the dielectric cap is located on a second side of the first portion of the off-centered frontside gate contact structure.
4 . The semiconductor structure of claim 2 , wherein the gate cap pillar is composed of a dielectric material that is compositionally different from a dielectric material that provides the dielectric cap.
5 . The semiconductor structure of claim 1 , further comprising a frontside source/drain contact structure directly contacting the first source/drain region.
6 . The semiconductor structure of claim 5 , further comprising a middle-of-the-line (MOL) dielectric layer partially embedding both the frontside source/drain contact structure and the off-centered frontside gate contact structure.
7 . The semiconductor structure of claim 6 , further comprising a frontside back-end-of-the-line (BEOL) structure located on the MOL dielectric layer, wherein the frontside BEOL structure comprises initial interconnect levels including metal vias and metal lines.
8 . The semiconductor structure of claim 7 , wherein a first metal via/metal line combination is electrically connected to the frontside source/drain contact structure and a second first metal via/metal line combination is electrically connected to the off-centered frontside gate contact structure.
9 . The semiconductor structure of claim 1 , further comprising a backside interconnect structure in direct contact with the backside source/drain contact structure.
10 . The semiconductor structure of claim 1 , wherein the recessed gate spacer laterally separates the gate structure from the second source/drain region.
11 . The semiconductor structure of claim 10 , wherein the dielectric cap has a width that is greater than a width of the second source/drain region.
12 . The semiconductor structure of claim 11 , wherein the dielectric cap extends onto a surface of the recessed gate spacer that is positioned between the gate structure and the second source/drain region.
13 . The semiconductor structure of claim 12 , wherein the recessed gate spacer has a topmost surface that is coplanar with a topmost surface of the second source/drain region.
14 . The semiconductor structure of claim 1 , wherein the transistor is a nanosheet transistor, and the nanosheet transistors comprises a nanosheet stack comprising a plurality of vertically stacked and spaced apart semiconductor channel material nanosheets, wherein the gate structure wraps around a portion of each of the semiconductor channel material nanosheets of the plurality of vertically stacked and spaced apart semiconductor channel material nanosheets.
15 . The semiconductor structure of claim 1 , wherein the second source/drain region is a replacement source/drain region.