Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
1. A semiconductor device, comprising:
a die interconnect substrate, comprising:
a substrate structure comprising an electrically insulating substrate; and
a bridge die embedded in the electrically insulating substrate of the substrate structure, the bridge die comprising a silicon substrate, wherein a first portion of the electrically insulating substrate is on sidewalls of the bridge die and on a front side of the bridge die;
a lateral wire beneath the bridge die, the lateral wire extending an entirety of the bridge die, wherein a second portion of the electrically insulating substrate is beneath the lateral wire;
a first interface structure coupled to a first bridge die pad of the front side of the bridge die, the first interface structure through the first portion of the electrically insulating substrate;
a second interface structure coupled to a second bridge die pad of the front side of the bridge die, the second interface structure through the first portion of the electrically insulating substrate;
a first substrate interconnect through the first portion of the electrically insulating substrate; and
a second substrate interconnect through the first portion of the electrically insulating substrate; and
a first die coupled to the bridge die by the first interface structure, the first die also coupled to the first substrate interconnect, wherein the first die is coupled to the lateral wire; and
a second die coupled to the bridge die by the second interface structure, the second die also coupled to the second substrate interconnect, wherein the second die is coupled to the lateral wire.
2. The semiconductor device of claim 1 , wherein the first die is a memory die.
3. The semiconductor device of claim 1 , wherein the first die is a processor die.
4. The semiconductor device of claim 1 , wherein the first die is a memory die, and the second die is a processor die.
5. The semiconductor device of claim 1 , wherein the first bridge die pad of the front side of the bridge die is electrically coupled to the second bridge die pad of the front side of the bridge die.
6. The semiconductor device of claim 1 , wherein the first and second substrate interconnects each have a bottom surface below a bottom surface of the bridge die.
7. The semiconductor device of claim 1 , wherein the electrically insulating substrate comprises an electrically insulating core.
8. The semiconductor device of claim 1 , wherein the electrically insulating substrate is a polymer-based substrate.
9. The semiconductor device of claim 1 , wherein the electrically insulating substrate is an epoxy-based substrate.
10. The semiconductor device of claim 1 , wherein the electrically insulating substrate is a laminate-based substrate.
11. A semiconductor device, comprising:
a die interconnect substrate, comprising:
a substrate structure; and
a bridge die embedded in the substrate structure, the bridge die comprising a silicon substrate;
a lateral wire beneath the bridge die, the lateral wire extending an entirety of the bridge die, wherein a portion of the substrate structure is beneath the lateral wire;
a first interface structure coupled to a first bridge die pad of the bridge die;
a second interface structure coupled to a second bridge die pad of the bridge die;
a first substrate interconnect at a first side of the bridge die, the first substrate interconnect electrically insulated from the bridge die; and
a second substrate interconnect at a second side of the bridge die, the second substrate interconnect electrically insulated from the bridge die; and
a first die coupled to the bridge die by the first interface structure, the first die also coupled to the first substrate interconnect, wherein the first die is coupled to the lateral wire; and
a second die coupled to the bridge die by the second interface structure, the second die also coupled to the second substrate interconnect, wherein the second die is coupled to the lateral wire.
12. The semiconductor device of claim 11 , wherein the first die is a memory die.
13. The semiconductor device of claim 11 , wherein the first die is a processor die.
14. The semiconductor device of claim 11 , wherein the first die is a memory die, and the second die is a processor die.
15. The semiconductor device of claim 11 , wherein the first bridge die pad of the bridge die is electrically coupled to the second bridge die pad of the bridge die.
16. The semiconductor device of claim 11 , wherein the first and second substrate interconnects each have a bottom surface below a bottom surface of the bridge die.
17. The semiconductor device of claim 11 , wherein the substrate structure comprises an electrically insulating core.
18. The semiconductor device of claim 11 , wherein the substrate structure is a polymer-based substrate structure.
19. The semiconductor device of claim 11 , wherein the substrate structure is an epoxy-based substrate structure.
20. The semiconductor device of claim 11 , wherein the substrate structure is a laminate-based substrate structure.