Semiconductor package with local interconnect and chiplet integration
Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.
1 . A semiconductor package comprising:
a first die;
a second die; and
a local interconnect electrically connecting the first die and the second die, wherein the local interconnect includes a base layer and a routing layer supported by the base layer, the routing layer including a metal wire spanning across a cavity in the routing layer;
wherein a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the cavity.
2 . The semiconductor package of claim 1 , wherein the base layer is a silicon layer.
3 . The semiconductor package of claim 1 , wherein the routing layer includes a plurality of support walls, and the metal wire extends through the plurality of support walls.
4 . The semiconductor package of claim 1 , wherein the cavity is an air cavity.
5 . The semiconductor package of claim 1 , wherein the cavity is filled with a material characterized by a dielectric constant less than 3.
6 . The semiconductor package of claim 1 , wherein the base layer includes a plurality of deep trench capacitors.
7 . The semiconductor package of claim 1 , wherein the routing layer includes a metal-insulator-metal (MIM) capacitor.
8 . The semiconductor package of claim 1 , wherein the cavity is both over and underneath the metal wire spanning across the cavity.
9 . The semiconductor package of claim 8 , further comprising a second routing layer over the routing layer, wherein the second routing layer comprise a metal-insulator-metal (MIM) capacitor.
10 . The semiconductor package of claim 8 , further comprising a second routing layer over the routing layer and a second base layer between the second routing layer and the routing layer.
11 . The semiconductor package of claim 8 , further comprising a second routing layer over the routing layer and a second base layer, wherein the second routing layer is bonded to the routing layer, and the second base layer is on an opposite side of the second routing layer than the routing layer.
12 . The semiconductor package of claim 8 , further comprising a second routing layer over the routing layer and a plurality of deep trench capacitors in the routing layer or the second routing layer, and a plurality of active devices in the base layer.
13 . The semiconductor package of claim 1 :
wherein the first die includes a first plurality of contact pads over a first input/output region along a central axis of the first die, and a second plurality of contact pads over a second input/output region of the first die;
further comprising a redistribution layer (RDL) spanning over the first die, the redistribution layer including a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads with a fanout wiring;
wherein the local interconnect is connected to the plurality of landing pads of the RDL; and
wherein the local interconnect is characterized by a longitudinal length spanning across the first die, and the fanout wiring of the RDL is orthogonal to the longitudinal length.
14 . The semiconductor package of claim 13 , wherein:
the metal wire of the local interconnect spans along the longitudinal length;
the local interconnect is a communication bar;
the local interconnect is connected a first core region of the first die to a second core region of the first die; and
the local interconnect includes active devices.
15 . The semiconductor package of claim 1 :
wherein the local interconnect is part of a plurality of separate local interconnects electrically connecting the first die and the second die, wherein each separate local interconnect includes a base layer and a routing layer supported by the base layer, the routing layer including die-to-die routing electrically connecting the first die and the second die.
16 . The semiconductor package of claim 15 , wherein the plurality of separate local interconnects includes a first local interconnect characterized by a first longitudinal length spanning across the first die and the second die, and a second local interconnect characterized by a second longitudinal length spanning across the first die and the second die, wherein the second longitudinal length is longer than the first longitudinal length.
17 . A semiconductor package comprising:
a first die including a first plurality of contact pads over a first input/output region adjacent a first edge of the first die;
a second die including a second plurality of contact pads over a second input/output region adjacent a second edge of the second die;
a redistribution layer (RDL) spanning over the first die and the second die, the redistribution layer including a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads, wherein the plurality of landing pads is characterized by a larger pad pitch between pads than the first plurality of contact pads and the second plurality of contact pads; and
a local interconnect bonded to the plurality of landing pads of the RDL.
18 . The semiconductor package of claim 17 , wherein a first portion of the plurality of landing pads spans over a first logic region of the first die.
19 . The semiconductor package of claim 17 , wherein the local interconnect includes a base layer and a routing layer supported by the base layer, the routing layer including a metal wire spanning across a cavity in the routing layer.
20 . A semiconductor package comprising:
a first die including a first plurality of contact pads over a first input/output region along a central axis of the first die;
a second die including a second plurality of contact pads over a second input/output region of the second die;
a redistribution layer (RDL) spanning over the first die and the second die, the redistribution layer including a plurality of landing pads electrically connected to the first plurality of contact pads and the second plurality of contact pads with a fanout wiring; and
a local interconnect connected to the plurality of landing pads of the RDL;
wherein the local interconnect is characterized by a longitudinal length spanning across the first die and the second die, and the fanout wiring of the RDL extends in a direction that is orthogonal to the longitudinal length and toward a die edge of the first die that is parallel to the longitudinal length.
21 . The semiconductor package of claim 20 , wherein the local interconnect includes die-to-die wiring along the longitudinal length.
22 . The semiconductor package of claim 20 , wherein the local interconnect is a communication bar.
23 . The semiconductor package of claim 20 , wherein the local interconnect is connected a first core region of the first die to a second core region of the second die.
24 . The semiconductor package of claim 20 , wherein the local interconnect includes active devices.
25 . The semiconductor package of claim 20 , further comprising an active die adjacent the local interconnect, and underneath the first die to provide communication function to the first die.
26 . The semiconductor package of claim 20 , further comprising an integrated passive device adjacent the local interconnect, and underneath the second die.