High density interconnection using fanout interposer chiplet

1. A package comprising:

an encapsulation layer;

an interposer chiplet embedded within the encapsulation layer;

a plurality of conductive pillars embedded within the encapsulation layer; and

a redistribution layer (RDL) spanning over a first side of the encapsulation layer;

a first component and a second component mounted on a first side of the RDL opposite the encapsulation layer;

wherein a first plurality of terminals of the first and second components are in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components are in electrical connection with the interposer chiplet through an arrangement of a plurality of interconnects extending through the RDL, each interconnect including a plurality of stacked vias that are stacked in direct contact with one another.

2. The package of claim 1 , wherein the RDL comprises a first area of fan out interconnect routing interconnected with the plurality of conductive pillars.

3. The package of claim 2 , further comprising a plurality of contact pads on the first side of the RDL, wherein the first and second components are bonded to the plurality of contact pads.

4. The package of claim 3 , further comprising a first plurality of conductive bumps connecting the first and second components to the fan out interconnect routing of the RDL, and a second plurality of conductive bumps connecting the first and second components to the arrangement of stacked vias extending through the RDL.

5. The package of claim 4 , wherein the first plurality of conductive bumps has a larger pitch than the second plurality of conductive bumps.

6. The package of claim 5 , wherein the second plurality of conductive bumps are smaller than the first plurality of conductive bumps.

7. The package of claim 1 , wherein the first component is selected from the group consisting of a first die and a first package, and the second component is selected from the group consisting of a second die and a second package.

8. The package of claim 1 , wherein the interposer chiplet interconnects the first and second components.

9. The package of claim 8 , wherein:

the RDL comprises a first area of fan out interconnect routing interconnected with the plurality of conductive pillars; and

the interposer chiplet includes interposer routing characterized by a finer pitch than the first area of fan out interconnect routing.

10. The package of claim 1 , further comprising a back side RDL on the encapsulation layer opposite the RDL.

11. The package of claim 10 , wherein the back side RDL includes redistribution lines connected to the plurality of conductive pillars.

12. The package of claim 11 , wherein the back side RDL includes a plurality of under bump metallurgy (UBM) pads.

13. The package of claim 12 , further comprising a plurality of back side conductive bumps on the plurality of UBM pads.

14. A method of forming a package comprising:

forming a plurality of conductive pillars on a carrier substrate;

attaching an interposer chiplet to the carrier substrate adjacent the plurality of conductive pillars;

encapsulating the interposer chiplet and the plurality of conductive pillars within an encapsulation layer;

forming a redistribution layer (RDL) over and in electrical contact with the encapsulated interposer chiplet and the plurality of conductive pillars, wherein forming the RDL comprises forming a first area of fan out interconnect routing interconnected with the plurality of conductive pillars, and an arrangement of a plurality of interconnects extending through the RDL, each interconnect including a plurality of stacked vias that are stacked in direct contact with one another and are interconnected with the interposer chiplet;

mounting a first component and a second component on the RDL and in electrical connection with the first area of fan out interconnect routing and the arrangement of stacked vias; and

removing the carrier substrate.

15. The method of claim 14 , wherein encapsulating the interposer chiplet and the plurality of conductive pillars comprises depositing a molding compound, and planarizing the molding compound to expose the plurality of conductive pillars and landing pads of the interposer chiplet.

16. The method of claim 14 , wherein the interposer chiplet includes interposer routing characterized by a finer pitch than the first area of fan out interconnect routing.

17. The method of claim 14 , wherein the first component is selected from the group consisting of a first die and a first package, and the second component is selected from the group consisting of a second die and a second package.

18. The method of claim 14 , wherein mounting the first component and the second component on the RDL comprises mounting the first component and the second component with a first plurality of conductive bumps connecting the first and second components to the fan out interconnect routing of the RDL, and a second plurality of conductive bumps connecting the first and second components to the arrangement of stacked vias extending through the RDL.

19. The method of claim 18 , wherein the first plurality of conductive bumps has a larger pitch than the second plurality of conductive bumps.

20. The method of claim 19 , wherein the second plurality of conductive bumps are smaller than the first plurality of conductive bumps.