Integrated circuit device and method of manufacturing the same

1. An integrated circuit device comprising:

a fin-type active area comprising a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface;

a nanosheet stack facing the fin top surface at a location apart from the fin top surface, the nanosheet stack comprising a plurality of nanosheets having vertical distances different from each other from the fin top surface;

a gate structure surrounding each of the plurality of nanosheets;

a source/drain region having a side wall facing at least one of the plurality of nanosheets; and

an anti-punch-through semiconductor layer comprising a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.

2. The integrated circuit device of claim 1 , wherein

the source/drain region comprises a doped semiconductor layer, and the anti-punch-through semiconductor layer comprises an undoped semiconductor layer.

3. The integrated circuit device of claim 1 , wherein

the source/drain region comprises a first semiconductor layer doped with a first dopant of a first conductivity type, and the anti-punch-through semiconductor layer comprises a second semiconductor layer doped with a second dopant of a second conductivity type that is opposite to the first conductivity type.

4. The integrated circuit device of claim 1 , wherein

the anti-punch-through semiconductor layer is in contact with a side wall of at least one nanosheet at a level higher than that of the first nanosheet among the plurality of nanosheets, and

the source/drain region is apart from the nanosheet stack with the anti-punch-through semiconductor layer interposed therebetween.

5. The integrated circuit device of claim 1 , wherein

a level of a top surface of the first portion of the anti-punch-through semiconductor layer is equal to or lower than the level of the fin top surface.

6. The integrated circuit device of claim 1 , wherein

a level of a top surface of a portion, which vertically overlaps a lowermost portion of the anti-punch-through recess, of the anti-punch-through semiconductor layer is higher than the level of the fin top surface.

7. The integrated circuit device of claim 1 , wherein

the anti-punch-through semiconductor layer is apart from at least one nanosheet comprising an uppermost nanosheet among the plurality of nanosheets, and

the source/drain region is in contact with the at least one nanosheet comprising the uppermost nanosheet.

8. The integrated circuit device of claim 1 , wherein

the source/drain region comprises a plurality of semiconductor layers having different dopant concentrations from each other and has a relatively low dopant concentration toward the anti-punch-through semiconductor layer and a relatively high dopant concentration away from the anti-punch-through semiconductor layer.

9. The integrated circuit device of claim 1 , wherein

the first portion of the anti-punch-through semiconductor layer comprises a portion vertically overlapping the nanosheet stack.

10. An integrated circuit device comprising:

a fin-type active area protruding from a substrate, extending in a first horizontal direction, and having a fin top surface;

a pair of nanosheet stacks facing the fin top surface at a location apart from the fin top surface, the pair of nanosheet stacks each comprising a plurality of nanosheets having vertical distances different from each other from the fin top surface;

a pair of gate structures respectively covering the pair of nanosheet stacks and extending in a second horizontal direction perpendicular to the first horizontal direction;

a source/drain region disposed between the pair of nanosheet stacks;

an anti-punch-through recess formed in a top portion of the fin-type active area between the pair of nanosheet stacks, and having a bottom surface thereof at a level lower than a level of the fin top surface; and

an anti-punch-through semiconductor layer comprising a first portion filling the anti-punch-through recess between the fin-type active area and the source/drain region, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.

11. The integrated circuit device of claim 10 , wherein

the anti-punch-through semiconductor layer is in contact with the source/drain region, and a lowermost level of an interface between the anti-punch-through semiconductor layer and the source/drain region is equal to or lower than the level of the fin top surface.

12. The integrated circuit device of claim 10 , wherein

the anti-punch-through semiconductor layer is in contact with the source/drain region, and a lowermost level of an interface between the anti-punch-through semiconductor layer and the source/drain region is higher than the level of the fin top surface.

13. The integrated circuit device of claim 10 , wherein

the anti-punch-through semiconductor layer further comprises a second portion in contact with a side wall of at least one of the pair of nanosheet stacks.

14. The integrated circuit device of claim 10 , wherein

the anti-punch-through semiconductor layer comprises an undoped semiconductor layer.

15. The integrated circuit device of claim 10 , wherein

the source/drain region comprises a first semiconductor layer doped with a first dopant of a first conductivity type, and the anti-punch-through semiconductor layer comprises a second semiconductor layer doped with a second dopant of a second conductivity type that is opposite to the first conductivity type.

16. The integrated circuit device of claim 10 , wherein

the anti-punch-through semiconductor layer comprises a first vertical extension portion integrally connected to the first portion and being in contact with a side wall of one nanosheet stack selected from the pair of nanosheet stacks, and a second vertical extension portion being in contact with a side wall of an other nanosheet stack selected from the pair of nanosheet stacks.

17. The integrated circuit device of claim 10 , wherein

the anti-punch-through semiconductor layer has a U-shaped cross-section shape on a cross-section in the first horizontal direction.

18. An integrated circuit device comprising:

a first fin-type active area protruding from a substrate in a first region of the substrate, and having a first fin top surface on a top portion thereof and a first anti-punch-through recess having a lowermost level lower than a level of the first fin top surface;

a first nanosheet stack facing the first fin top surface and comprising a plurality of nanosheets;

a first gate structure covering the first nanosheet stack;

a first source/drain region having a side wall facing the first nanosheet stack;

a first anti-punch-through semiconductor layer filling the first anti-punch-through recess between the first fin-type active area and the first source/drain region, the first anti-punch-through semiconductor layer comprising a material different from a material of the first source/drain region;

a second fin-type active area protruding from the substrate in a second region of the substrate, and having a second fin top surface on a top portion thereof and a second anti-punch-through recess having a lowermost level lower than a level of the second fin top surface;

a second nanosheet stack facing the second fin top surface and comprising a plurality of nanosheets;

a second gate structure covering the second nanosheet stack;

a second source/drain region having a side wall facing the second nanosheet stack; and

a second anti-punch-through semiconductor layer filling the second anti-punch-through recess between the second fin-type active area and the second source/drain region, the second anti-punch-through semiconductor layer comprising a material different from a material of the second source/drain region,

wherein a first lowermost level of the first anti-punch-through semiconductor layer is different from a second lowermost level of the second anti-punch-through semiconductor layer.

19. The integrated circuit device of claim 18 , wherein

the first region comprises an n-type metal-oxide-semiconductor (NMOS) transistor region, the second region comprises a p-type metal-oxide-semiconductor (PMOS) transistor region, and the second lowermost level is lower than the first lowermost level.

20. The integrated circuit device of claim 18 , wherein

the first region comprises an NMOS transistor region and the second region comprises a PMOS transistor region, and

a lowermost level of an interface between the second anti-punch-through semiconductor layer and the second source/drain region is lower than a lowermost level of an interface between the first anti-punch-through semiconductor layer and the first source/drain region.