IP Library Granted Patent US 10,877,917
Granted Patent B2
US 10,877,917 · App. 16/593,508 · Granted Dec 29, 2020

Semiconductor device and memory system

Inventors: Kunihiko Yamagishi (Kanagawa, JP); Toshitada Saito (Kanagawa, JP)
Assignee: Toshiba Memory Corporation
G06F13/4068G06F12/0246G06F13/385G06F13/40G06F13/4063G06F13/42G06F13/4282H04L25/03828G06F2212/7201G06F2213/3804G06F2213/3854
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,877,917
App. No.
16/593,508
Granted
Dec 29, 2020
Kind
B2
Abstract

A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Claims (47)

1. A method of controlling a memory card by a memory controller circuit, the memory card comprising a card, a plurality of signal pins provided on the card and connectable to a host apparatus, a memory provided in the card and from and into which data can be read and written, and the memory controller circuit provided in the card and coupled to the memory and configured to be coupled to the host apparatus via ones of the plurality of pins, the method comprising:

selecting by the memory controller circuit one symbol from a pair of a first symbol and a second symbol;

performing 8b/10b coding for the selected symbol; and

transmitting the 8b/10b coded symbol to the host apparatus,

wherein

the first symbol has a plus running disparity and the second symbol has a minus running disparity, and

the one symbol selected by the memory controller circuit has a running disparity different from a running disparity of a symbol which is most recently selected.

2. The method according to claim 1 , wherein data to be transmitted from the card to the host apparatus is scrambled, and the scrambled data is transmitted to the host apparatus.

3. The method according to claim 1 , wherein the memory controller circuit selects one of the first and second symbols according to a random number.

4. The method according to claim 2 , wherein the memory controller circuit transmits, to the host apparatus, the coded symbol and coded scramble data as one symbol set.

5. A method of controlling a memory card by a memory controller circuit, the memory card comprising a card, a plurality of signal pins provided on the card and connectable to a host apparatus, a memory provided in the card and from and into which data can be read and written, and the memory controller circuit provided in the card and coupled to the memory and configured to be coupled to the host apparatus via ones of the plurality of pins, the method comprising:

selecting by the memory controller circuit one symbol from a pair of a first symbol and a second symbol;

performing 8b/10b coding for the selected symbol and a third symbol which indicates a delimiter; and

transmitting a symbol set,

wherein

the symbol set including the 8b/10b coded one of the first and second symbols and the 8b/10b coded third symbol is repeatedly transmitted to the host apparatus,

the symbol set is used to set up synchronization with the host apparatus,

the first symbol has a plus running disparity and the second symbol has a minus running disparity, and

the one symbol selected by the memory controller circuit has a ruining disparity different from a running disparity of a symbol which is most recently selected.

6. The method according to claim 5 , wherein data to be transmitted from the card to the host apparatus is scrambled, and the scrambled data is transmitted to the host apparatus.

7. The method according to claim 5 , wherein the memory controller circuit selects one of the first and second symbols according to a random number.

8. The method according to claim 6 , wherein the memory controller circuit transmits, to the host apparatus, the coded symbol and coded scramble data as one symbol set.

9. A method of controlling a memory card by a memory controller circuit,

the memory card comprising a card, a plurality of signal pins provided on the card and connectable to a host apparatus, a memory provided in the card and from and into which data can be read and written, and the memory controller circuit provided in the card and coupled to the memory and configured to be coupled to the host apparatus via ones of the plurality of pins, the method comprising:

selecting by the memory controller circuit one symbol from a pair of a first symbol and a second symbol, the symbols indicating an idle state;

performing 8b/10b coding for the selected symbol; and

transmitting the 8b/10b coded symbol to the host apparatus,

wherein

the first and second symbols indicate an idle state,

the 8b/10b coded symbol is repeatedly transmitted to the host apparatus,

one of the first and second symbols is a symbol in which a running disparity is ±0, and

the one symbol selected by the memory controller circuit has a running disparity different from a running disparity of a symbol which is most recently selected.

10. The method according to claim 9 , wherein data to be transmitted from the card to the host apparatus is scrambled, and the scrambled data is transmitted to the host apparatus.

11. The method according to claim 9 , wherein the memory controller circuit selects one of the first and second symbols according to a random number.

12. The method according to claim 10 , wherein the memory controller circuit transmits, to the host apparatus, the coded symbol and coded scramble data as one symbol set.

13. A method of controlling a memory card by a memory controller circuit, the memory card comprising a card, a plurality of signal pins provided on the card and connectable to a host apparatus, a memory provided in the card and from and into which data can be read and written, and the memory controller circuit provided in the card and coupled to the memory and configured to be coupled to the host apparatus via ones of the plurality of pins, the method comprising:

selecting by the memory controller circuit one symbol from a pair of a first symbol and a second symbol;

performing 8b/10b coding for the selected symbol and a third symbol which indicates a delimiter; and

transmitting a symbol set to the host apparatus,

wherein

the symbol set including the 8b/10b coded one of the first and second symbols and the 8b/10b coded third symbol is repeatedly transmitted to the host apparatus,

the symbol set is used to set up synchronization with the host apparatus,

one of the first and second symbols is a symbol in which a running disparity is ±0,

the one symbol selected by the memory controller circuit has a running disparity different from a running disparity of a symbol which is most recently selected.

14. The method according to claim 13 , wherein data to be transmitted from the card to the host apparatus is scrambled, and the scrambled data is transmitted to the host apparatus.

15. The method according to claim 13 , wherein the memory controller circuit selects one of the first and second symbols according to a random number.

16. The method according to claim 14 , wherein the memory controller circuit transmits, to the host apparatus, the coded symbol and coded scramble data as one symbol set.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Jul 29, 2021
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 057016/0551 →
MERGER Recorded Jul 29, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 057016/0586 →
CHANGE OF NAME AND ADDRESS Recorded Jul 29, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 057016/0611 →
Priority Claims (1)
JP 2009-279719 · Dec 9, 2009 · national
Continuity (7)
Continuation 15978272 · May 14, 2018
Continuation 15627821 · Jun 20, 2017
Continuation 15257666 · Sep 6, 2016
Continuation 14797970 · Jul 13, 2015
Continuation 14292180 · May 30, 2014
Continuation 13514736
Related Publication 20200034324A1 · Jan 30, 2020