IP Library › Granted Patent US 11,101,302
Granted Patent B2
US 11,101,302 · App. 16/615,156 · Granted Aug 24, 2021

Imaging device and electronic device

Inventors: Takayuki Ikeda (Kanagawa, JP); Yoshiyuki Kurokawa (Kanagawa, JP); Shintaro Harada (Kanagawa, JP); Hidetomo Kobayashi (Kanagawa, JP); Roh Yamamoto (Toyama, JP); Kiyotaka Kimura (Kanagawa, JP); Takashi Nakagawa (Kanagawa, JP); Yusuke Negoro (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/14605H01L27/1225H01L27/14612H01L27/14643H01L29/7869H04N5/341H04N5/3741H04N5/3745
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,101,302
App. No.
16/615,156
Granted
Aug 24, 2021
Kind
B2
Abstract

An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.

Claims (50)

1. An imaging device comprising:

a pixel block;

a first circuit; and

a second circuit,

wherein the pixel block comprises a plurality of pixels and a third circuit,

wherein the pixels and the third circuit are electrically connected to each other through a first wiring,

wherein the pixels have a function of obtaining a first signal by photoelectric conversion,

wherein the pixels have a function of multiplying the first signal by a predetermined multiplication factor to generate second signals and outputting the second signals to the first wiring,

wherein the third circuit has a function of calculating a sum of the second signals output to the first wiring to generate a third signal and outputting the third signal to the first circuit, and

wherein the first circuit binarizes the third signal to generate a fourth signal and outputs the fourth signal to the second circuit.

2. The imaging device according to claim 1 ,

wherein the second circuit has a function of performing parallel-serial conversion on the fourth signal.

3. The imaging device according to claim 1 ,

wherein the second circuit comprises a neural network which uses the fourth signal as input data.

4. The imaging device according to claim 1 ,

wherein the plurality of pixels are arranged in a matrix and any one column is shielded from light.

5. The imaging device according to claim 1 ,

wherein the pixels each comprise a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor,

wherein one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor,

wherein the gate of the third transistor is electrically connected to one electrode of the first capacitor,

wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,

wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the fourth transistor, and

wherein the first and second transistors comprise a metal oxide in their channel formation regions.

6. The imaging device according to claim 5 , further comprising:

a fifth transistor; and

a sixth transistor,

wherein a gate of the fifth transistor is electrically connected to the gate of the third transistor, and

wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor.

7. The imaging device according to claim 5 ,

wherein the third and fourth transistors comprise silicon in their channel formation regions.

8. The imaging device according to claim 1 ,

wherein the third circuit comprises a current supply circuit, a seventh transistor, an eighth transistor, a ninth transistor, a second capacitor, and a resistor,

wherein the current supply circuit is electrically connected to the first wiring,

wherein the first wiring is electrically connected to one electrode of the second capacitor,

wherein the one electrode of the second capacitor is electrically connected to one electrode of the resistor,

wherein the other electrode of the second capacitor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the seventh transistor is electrically connected to a gate of the eighth transistor, and

wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor.

9. The imaging device according to claim 8 ,

wherein the seventh to ninth transistors comprise silicon in their channel formation regions.

10. The imaging device according to claim 5 ,

wherein the metal oxide comprises In, Zn, and M,

wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

11. The imaging device according to claim 5 ,

wherein the photoelectric conversion element comprises selenium or a compound containing selenium.

12. An electronic device comprising:

the imaging device according to claim 1 ; and

a display device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2019
From: IKEDA, TAKAYUKI; KUROKAWA, YOSHIYUKI; HARADA, SHINTARO; KOBAYASHI, HIDETOMO; YAMAMOTO, ROH; KIMURA, KIYOTAKA; NAKAGAWA, TAKASHI; NEGORO, YUSUKE
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 051061/0649 →
Priority Claims (2)
JP 2017-104338 · May 26, 2017 · national
JP 2018-040915 · Mar 7, 2018 · national
Continuity (2)
Related Publication 20200176493A1 · Jun 4, 2020
Related Publication 20210134860A9 · May 6, 2021
Cited By (9)
US 12,205,965 US 12,211,584 US 12,225,314 US 12,238,435 US 12,354,636 US 12,376,447 US 12,389,608 US 12,585,431 US 12,659,621