Display panel with bendable edge portion and display device including display panel thereof

1. A display panel, comprising:

a substrate layer;

a thin film transistor (TFT) layer, wherein the TFT layer is disposed on the substrate layer, and a bending region is disposed on at least one side of the substrate layer near the TFT layer;

a gate on array (GOA) drive circuit, wherein the GOA drive circuit is disposed on the substrate layer and is disposed beside at least one side of the TFT layer, and the bending region is disposed between the GOA drive circuit and the TFT layer;

an auxiliary circuit, wherein the auxiliary circuit is disposed on the substrate layer and is disposed correspondingly to the bending region;

a voltage source supply (VSS) wire, wherein the VSS wire is disposed correspondingly to the bending region, and a second insulating layer is disposed between the VSS wire and the auxiliary circuit;

a planarization layer, wherein the planarization layer covers the TFT layer, the VSS wire, and the substrate layer, and a through hole is defined on the planarization layer and exposes the VSS wire; and

a cathode layer, wherein the cathode layer is disposed on the planarization layer and is connected to the VSS wire by the through hole; and

wherein the GOA drive circuit is connected to a gate wire of the TFT layer by the auxiliary circuit.

2. The display panel of claim 1 , wherein the substrate layer comprises a substrate and a first insulating layer which are sequentially stacked; and

a side of the substrate layer near the auxiliary circuit is provided with a plurality of first notches, and the first notches are defined in the first insulating layer in the bending region.

3. The display panel of claim 2 , wherein the auxiliary circuit is disposed along a surface of the substrate layer and inner surfaces of the first notches.

4. The display panel of claim 1 , wherein the substrate layer comprises a substrate and a first insulating layer which are sequentially stacked;

a side of the substrate layer near the auxiliary circuit is provided with a second notch, and the second notch is defined in the first insulating layer in the bending region; and

the second notch is filled with an organic layer.

5. The display panel of claim 4 , wherein the auxiliary circuit is disposed along a surface of the substrate layer and a surface of the organic layer.

6. The display panel of claim 1 , wherein the auxiliary circuit comprises a plurality of auxiliary circuit wires connected to the GOA drive circuit and the gate wire of the TFT layer; and

the auxiliary circuit wires in the bending region are arranged in wires with a single row of holes, wires with multiple rows of holes, wavy wires, or bent wires.

7. The display panel of claim 1 , wherein the display panel further comprises:

a planarization layer, wherein the planarization layer covers the TFT layer, the VSS wire, and the substrate layer, and a through hole is defined on the planarization layer and exposes the VSS wire;

an anode layer, wherein the anode layer is disposed on the planarization layer and is connected to the VSS wire by the through hole; and

a cathode layer, wherein the cathode layer is disposed on the anode layer and is connected to the anode layer.

8. The display panel of claim 1 , wherein the VSS wire is arranged in a wire with a single row of holes, a wire with multiple rows of holes, a wavy wire, or a bent wire.

9. A display device, comprising a display panel;

wherein the display panel comprises:

a substrate layer;

a thin film transistor (TFT) layer, wherein the TFT layer is disposed on the substrate layer, and a bending region is disposed on at least one side of the substrate layer near the TFT layer;

a gate on array (GOA) drive circuit, wherein the GOA drive circuit is disposed on the substrate layer and is disposed beside at least one side of the TFT layer, and the bending region is disposed between the GOA drive circuit and the TFT layer;

an auxiliary circuit, wherein the auxiliary circuit is disposed on the substrate layer and is disposed correspondingly to the bending region;

a voltage source supply (VSS) wire, wherein the VSS wire is disposed correspondingly to the bending region, and a second insulating layer is disposed between the VSS wire and the auxiliary circuit;

a planarization layer, wherein the planarization layer covers the TFT layer, the VSS wire, and the substrate layer, and a through hole is defined on the planarization layer and exposes the VSS wire; and

a cathode layer, wherein the cathode layer is disposed on the planarization layer and is connected to the VSS wire by the through hole; and

wherein the GOA drive circuit is connected to a gate wire of the TFT layer by the auxiliary circuit.

10. The display device of claim 9 , wherein the substrate layer comprises a substrate and a first insulating layer which are sequentially stacked; and

a side of the substrate layer near the auxiliary circuit is provided with a plurality of first notches, and the first notches are defined in the first insulating layer in the bending region.

11. The display device of claim 10 , wherein the auxiliary circuit is disposed along a surface of the substrate layer and inner surfaces of the first notches.

12. The display device of claim 9 , wherein the substrate layer comprises a substrate and a first insulating layer which are sequentially stacked;

a side of the substrate layer near the auxiliary circuit is provided with a second notch, and the second notch is defined in the first insulating layer in the bending region; and

the second notch is filled with an organic layer.

13. The display device of claim 12 , wherein the auxiliary circuit is disposed along a surface of the substrate layer and a surface of the organic layer.

14. The display device of claim 9 , wherein the auxiliary circuit comprises a plurality of auxiliary circuit wires connected to the GOA drive circuit and the gate wire of the TFT layer; and

the auxiliary circuit wires in the bending region are arranged in wires with a single row of holes, wires with multiple rows of holes, wavy wires, or bent wires.

15. The display device of claim 9 , wherein the display panel further comprises:

a planarization layer, wherein the planarization layer covers the TFT layer, the VSS wire, and the substrate layer, and a through hole is defined on the planarization layer and exposes the VSS wire;

an anode layer, wherein the anode layer is disposed on the planarization layer and is connected to the VSS wire by the through hole; and

a cathode layer, wherein the cathode layer is disposed on the anode layer and is connected to the anode layer.

16. The display device of claim 9 , wherein the VSS wire is arranged in a wire with a single row of holes, a wire with multiple rows of holes, a wavy wire, or a bent wire.

17. A display panel, comprising:

a substrate layer;

a thin film transistor (TFT) layer, wherein the TFT layer is disposed on the substrate layer, and a bending region is disposed on at least one side of the substrate layer near the TFT layer;

a gate on array (GOA) drive circuit, wherein the GOA drive circuit is disposed on the substrate layer and is disposed beside at least one side of the TFT layer, and the bending region is disposed between the GOA drive circuit and the TFT layer;

an auxiliary circuit, wherein the auxiliary circuit is disposed on the substrate layer and is disposed correspondingly to the bending region;

a voltage source supply (VSS) wire, wherein the VSS wire is disposed correspondingly to the bending region, and a second insulating layer is disposed between the VSS wire and the auxiliary circuit;

a planarization layer, wherein the planarization layer covers the TFT layer, the VSS wire, and the substrate layer, and a through hole is defined on the planarization layer and exposes the VSS wire;

an anode layer, wherein the anode layer is disposed on the planarization layer and is connected to the VSS wire by the through hole; and

a cathode layer, wherein the cathode layer is disposed on the anode layer and is connected to the anode layer; and

wherein the GOA drive circuit is connected to a gate wire of the TFT layer by the auxiliary circuit.