Granted Patent B2

US 12,727,341 · App. 18/037,138 · Granted Sep 1, 2026

Inventors: Haohui Long (Shenzhen, CN); Xiaolong Li (Shenzhen, CN); Shi Zhang (Shenzhen, CN); Jianping Fang (Shenzhen, CN); Shanshan Wei (Shenzhen, CN); Yingbo Zhao (Shenzhen, CN)

Assignee: Honor Device Co., Ltd.

H10K59/124H10K59/1201H10K59/131

Abstract

Claims (54)

1 . A display panel, comprising: a display region and a non-display region extending around the display region, wherein the display panel comprises:

a base;

an array structure layer, disposed on the base, wherein a drive circuit is disposed in the array structure layer, the array structure layer comprises a first portion and a second portion, the first portion is a projection portion of the display region on the array structure layer, the second portion is a projection portion of the non-display region on the array structure layer, the second portion is provided with a groove, and the groove is filled with a first organic material;

an organic planarization layer, wherein the organic planarization layer covers the first portion and comprises the first organic material;

a light-emitting component layer, disposed on the organic planarization layer, wherein the light-emitting component layer corresponds to the display region and is electrically connected to the drive circuit; and

a packaging layer, wherein the packaging layer covers the light-emitting component layer and extends to the second portion, and the packaging layer covers the groove and the first organic material in the groove, and

wherein the second portion comprises an insulation layer, a buffer layer, a gate insulation layer, and an inter-layer dielectric layer that are stacked in sequence, and all of the insulation layer, the buffer layer, the gate insulation layer, and the inter-layer dielectric layer are inorganic film layers, the organic planarization layer is stacked on and in contact with a surface of the inter-layer dielectric layer, an end of the groove is aligned with the surface of the inter-layer dielectric layer, and the first organic material in the groove is surrounded by and in contact with the inter-layer dielectric layer.

2 . The display panel according to claim 1 , further comprising:

a signal cable layer, disposed on the array structure layer, wherein the signal cable layer is provided with a signal cable on the second portion, and the groove corresponds to a position of the signal cable.

3 . The display panel according to claim 2 , wherein the signal cable comprises a voltage of source series (VSS) signal cable.

4 . The display panel according to claim 1 , wherein the groove partially or completely penetrates the array structure layer.

5 . The display panel according to claim 1 , wherein the gate insulation layer comprises a first gate insulation layer and a second gate insulation layer that are stacked, the organic planarization layer comprises a first planarization layer and a second planarization layer, the first planarization layer comprises the first organic material, the first portion of the array structure layer is provided with a thin-film transistor layer, and the thin-film transistor layer comprises an active layer, a gate, and a source/drain, wherein

the active layer is disposed between the buffer layer and the first gate insulation layer, and the first gate insulation layer coats the active layer and extends to the buffer layer;

the gate is disposed between the first gate insulation layer and the second gate insulation layer, the second gate insulation layer coats the gate and extends to the first gate insulation layer, and the gate is disposed opposite the active layer;

the source/drain comprises a first source/drain portion and a second source/drain portion, wherein

the first source/drain portion is disposed between the inter-layer dielectric layer and the first planarization layer, the first planarization layer coats the first source/drain portion, the first organic material of the first planarization layer is filled in the groove, and the first source/drain portion is connected to the active layer after sequentially penetrating the inter-layer dielectric layer, the second gate insulation layer, and the first gate insulation layer;

the second source/drain portion is disposed between the first planarization layer and the second planarization layer, the second planarization layer coats the second source/drain portion and extends to the first planarization layer, and the second source/drain portion is connected to the first source/drain portion after penetrating the first planarization layer; and

a first signal cable portion is disposed in a region, corresponding to the groove, of the inter-layer dielectric layer, wherein the first signal cable portion is a signal cable fabricated on the same layer as the second source/drain portion, and the first signal cable portion covers the first organic material filled in the groove and the inter-layer dielectric layer around the groove.

6 . The display panel according to claim 5 , wherein the light-emitting component layer comprises an anode, an organic light-emitting layer, and a cathode that are stacked, wherein

the anode is disposed on the second planarization layer, and is connected to the second source/drain portion after penetrating the second planarization layer;

a second signal cable portion is disposed on the first signal cable portion, is connected to the first signal cable portion, and is a signal cable fabricated on the same layer as the anode; and

the cathode is disposed on the organic light-emitting layer, covers the organic light-emitting layer, and extends to the second signal cable portion.

7 . The display panel according to claim 6 , wherein the first signal cable portion and the second signal cable portion are part of a voltage of source series (VSS) signal cable.

8 . The display panel according to claim 1 , wherein

a shape of a section of the groove in a thickness direction of the display panel is any one of the following shapes:

a rectangle, a triangle, a trapezoid, a parallelogram, a polyline, a wave, an ellipse, an arc, or a stair; and/or

an extending direction of the groove in a plane where the display panel is located forms any of the following:

a straight line, a curve, or a ring.

9 . The display panel according to claim 1 , wherein the groove extends in an extending direction along an edge of the first portion, and the groove comprises consecutive trenches in the extending direction or intermittent trenches in the extending direction.

10 . The display panel according to claim 1 , wherein an average width of the groove ranges from 15 microns to 25 microns.

11 . The display panel according to claim 1 , wherein the groove comprises a plurality of parallel trenches, and the plurality of parallel trenches extend along an edge of the first portion, wherein

a distance between two adjacent trenches in the plurality of parallel trenches ranges from 20 microns to 25 microns.

12 . The display panel according to claim 11 , wherein a width of a trench in the plurality of parallel trenches that is close to the edge of the first portion is greater than or equal to a width of a trench in the plurality of parallel trenches that is close to an edge of the display panel.

13 . The display panel according to claim 1 , wherein a shortest distance between the groove and an edge of the display panel ranges from 200 microns to 250 microns.

14 . The display panel according to claim 1 , wherein the base is made of a flexible material.

15 . A display apparatus, comprising the display panel according to claim 1 .

16 . The display panel according to claim 1 , wherein the first organic material in the groove is in contact with the base.

17 . A fabrication method of a display panel, wherein the display panel comprises a display region and a non-display region extending around the display region, and the fabrication method comprises:

providing a base;

forming an array structure layer on the base, wherein a drive circuit is disposed in the array structure layer, the array structure layer comprises a first portion and a second portion, the first portion is a projection portion of the display region on the array structure layer, and the second portion is a projection portion of the non-display region on the array structure layer;

forming a groove in the second portion;

forming an organic planarization layer on the array structure layer, wherein the organic planarization layer covers the first portion and further comprises a first organic material, and the first organic material is filled in the groove;

wherein forming the array structure layer comprises sequentially forming an insulation layer, a buffer layer, an active layer, a gate insulation layer, a gate, and an inter-layer dielectric layer on the base, wherein the organic planarization layer is stacked on and in contact with a surface of the inter-layer dielectric layer, an end of the groove is aligned with the surface of the inter-layer dielectric layer, and the first organic material in the groove is surrounded by and in contact with the inter-layer dielectric layer;

forming a light-emitting component layer on the organic planarization layer, wherein the light-emitting component layer corresponds to the display region and is electrically connected to the drive circuit; and

forming a packaging layer on the light-emitting component layer, wherein the packaging layer covers the light-emitting component layer and extends to the second portion, and the packaging layer covers the groove and the first organic material in the groove.

18 . The fabrication method according to claim 17 , wherein the fabrication method further comprises:

forming a signal cable layer on the array structure layer, wherein the signal cable layer is provided with a signal cable on the second portion, and the groove corresponds to a position of the signal cable.

19 . The fabrication method according to claim 17 , wherein:

the active layer and the gate are disposed on the first portion, the gate insulation layer coats the active layer and extends to the buffer layer, and the inter-layer dielectric layer coats the gate and extends to the gate insulation layer; and

the forming a groove in the second portion comprises:

patterning the array structure layer to form a first hole in the first portion and form the groove in the second portion, wherein the first hole penetrates the inter-layer dielectric layer and the gate insulation layer and communicates with the active layer, and the groove partially or completely penetrates the inter-layer dielectric layer, the gate insulation layer, the buffer layer, and the insulation layer that are stacked in sequence.

20 . The fabrication method according to claim 17 , wherein the forming an organic planarization layer on the array structure layer comprises:

applying an organic film on the array structure layer, wherein the organic film covers the first portion and the second portion, and is filled in the groove; and

patterning the organic film to remove the organic film on the second portion of the array structure layer and retain the organic film filled in the groove.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (33)