Strained thin film transistors

1. An integrated circuit structure, comprising:

a strain inducing layer on an insulator layer above a substrate;

a polycrystalline channel material layer on the strain inducing layer, wherein the polycrystalline channel material layer is a non-planar and strained polycrystalline channel material layer;

a gate dielectric layer on a first portion of the polycrystalline channel material layer; and

a gate electrode on the gate dielectric layer, the gate electrode having a first side opposite a second side;

a first conductive contact adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material layer; and

a second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material layer.

2. The integrated circuit structure of claim 1 , wherein the strain inducing layer comprises a boron carbide (BC) material layer.

3. The integrated circuit structure of claim 1 , wherein the strain inducing layer comprises a silicon oxynitride (SiON) material layer.

4. The integrated circuit structure of claim 1 , wherein the polycrystalline channel material layer comprises a polycrystalline silicon material layer.

5. The integrated circuit structure of claim 1 , wherein the polycrystalline channel material layer comprises a polycrystalline Group III-V material layer.

6. The integrated circuit structure of claim 1 , wherein the polycrystalline channel material layer comprises a semiconducting oxide material layer.

7. The integrated circuit structure of claim 1 , wherein the gate dielectric layer comprises a layer of a high-k dielectric material.

8. An integrated circuit structure, comprising:

an insulator structure above a substrate, the insulator structure having a topography that varies along a plane parallel with a global plane of the substrate;

a strain inducing layer on the insulator structure, the strain inducing layer conformal with the topography of the insulator structure;

a channel material layer on the strain inducing layer, the channel material layer conformal with the topography of the insulator structure;

a gate electrode over a first portion of the channel material layer, the gate electrode having a first side opposite a second side; a first conductive contact adjacent the first side of the gate electrode, the first conductive contact on a second portion of the channel material layer; and

a second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the channel material layer.

9. The integrated circuit structure of claim 8 , wherein the insulator structure comprises one or more fins, individual ones of the fins having a top and sidewalls, the strain inducing layer on the top and sidewalls of the individual ones of the fins.

10. The integrated circuit structure of claim 8 , further comprising:

a gate dielectric layer between the gate electrode and the first portion of the channel material layer.

11. The integrated circuit structure of claim 10 , wherein the gate dielectric layer comprises a layer of a high-k dielectric material.

12. The integrated circuit structure of claim 8 , further comprising:

a first dielectric spacer between the first conductive contact and the first side of the gate electrode; and

a second dielectric spacer between the second conductive contact and the second side of the gate electrode.

13. The integrated circuit structure of claim 8 , wherein the strain inducing layer comprises a boron carbide (BC) material layer.

14. The integrated circuit structure of claim 8 , wherein the strain inducing layer comprises a silicon oxynitride (SiON) material layer.

15. The integrated circuit structure of claim 8 , wherein the channel material layer comprises a polycrystalline silicon material layer.

16. The integrated circuit structure of claim 8 , wherein the channel material layer comprises a polycrystalline Group III-V material layer.

17. The integrated circuit structure of claim 8 , wherein the channel material layer comprises a semiconducting oxide material layer.

18. An integrated circuit structure, comprising:

an insulator structure above a substrate, the insulator structure having a trench therein, the trench having sidewalls and a bottom; a strain inducing layer in the trench in the insulator structure, the strain inducing layer conformal with the sidewalls and bottom of the trench;

a channel material layer on the strain inducing layer in the trench;

a gate dielectric layer on the channel material layer in the trench;

a gate electrode on the gate dielectric layer in the trench, the gate electrode having a first side opposite a second side and having an exposed top surface;

a first conductive contact laterally adjacent the first side of the gate electrode; and

a second conductive contact laterally adjacent the second side of the gate electrode.

19. The integrated circuit structure of claim 18 , further comprising: a third conductive contact over and in contact with the exposed top surface of the gate electrode.

20. The integrated circuit structure of claim 18 , wherein the strain inducing layer comprises a boron carbide (BC) material layer.

21. The integrated circuit structure of claim 18 , wherein the strain inducing layer comprises a silicon oxynitride (SiON) material layer.

22. The integrated circuit structure of claim 18 , wherein the channel material layer comprises a polycrystalline silicon material layer.

23. The integrated circuit structure of claim 18 , wherein the channel material layer comprises a polycrystalline Group III-V material layer.

24. The integrated circuit structure of claim 18 , wherein the channel material layer comprises a semiconducting oxide material layer.