IP Library Granted Patent US 11,990,502
Granted Patent B2
US 11,990,502 · App. 16/638,825 · Granted May 21, 2024

Display device and electronic device

Inventors: Susumu Kawashima (Kanagawa, JP); Koji Kusunoki (Kanagawa, JP); Kazunori Watanabe (Tokyo, JP); Kouhei Toyotaka (Kanagawa, JP); Naoto Kusumoto (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10K59/1213G09G3/3275H10K50/11H10K59/1216H10K59/131G09G2300/0857G09G2310/0251G09G2310/0262
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Quick Facts
Patent No.
US 11,990,502
App. No.
16/638,825
Granted
May 21, 2024
Kind
B2
Abstract

To provide a display device capable of performing image processing. Each pixel is provided with a memory circuit in which desired correction data is retained. The correction data is generated by calculation in an external device and written to each pixel. The correction data is added to image data by capacitive coupling and supplied to a display element. Thus, the display element can display a corrected image. Through the correction, image upconversion can be performed, or image quality decreased because of variations in pixel transistor characteristics can be corrected.

Claims (29)

1. A display device comprising a pixel, the pixel comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, a second capacitor, and a display element,

wherein one of a source and a drain of the first transistor is electrically connected to a first electrode of the first capacitor,

wherein a second electrode of the first capacitor is electrically connected to one of a source and a drain of the second transistor, a gate of the third transistor, and a first electrode of the second capacitor,

wherein a second electrode of the second capacitor is electrically connected to one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one of a source and a drain of the fifth transistor,

wherein the second electrode of the second capacitor is electrically connected to the display element through the fourth transistor,

wherein another one of the source and the drain of the fourth transistor is electrically connected to the display element,

wherein another one of the source and the drain of the first transistor is electrically connected to a first wiring that supplies first data,

wherein another one of the source and the drain of the second transistor is electrically connected to a second wiring that supplies second data,

wherein another one of the source and the drain of the third transistor is electrically connected to a third wiring which is a power supply line,

wherein the first electrode of the first capacitor is not electrically connected to the second electrode of the second capacitor,

wherein another one of the source and the drain of the fifth transistor is electrically connected to a fourth wiring,

wherein a gate of the first transistor is electrically connected to a first scan line,

wherein a gate of the second transistor is electrically connected to a second scan line,

wherein a gate of the fourth transistor is electrically connected to a third scan line, and

wherein a gate of the fifth transistor is electrically connected to the first scan line.

2. The display device according to claim 1 ,

wherein the first data is image data, and

wherein the second data is correction data.

3. The display device according to claim 1 , wherein a channel formation region of the second transistor comprises a metal oxide comprising In and Zn.

4. The display device according to claim 1 , wherein a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises a metal oxide comprising In and Zn.

5. The display device according to claim 1 ,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises a back gate,

wherein the back gate of the first transistor is electrically connected to a gate of the first transistor,

wherein the back gate of the second transistor is electrically connected to a gate of the second transistor,

wherein the back gate of the third transistor is electrically connected to the gate of the third transistor,

wherein the back gate of the fourth transistor is electrically connected to a gate of the fourth transistor, and

wherein the back gate of the fifth transistor is electrically connected to a gate of the fifth transistor.

6. The display device according to claim 1 , wherein the display element is an EL element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2020
From: KAWASHIMA, SUSUMU; KUSUNOKI, KOJI; WATANABE, KAZUNORI; TOYOTAKA, KOUHEI; KUSUMOTO, NAOTO; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 051809/0187 →
Priority Claims (4)
JP 2017-166757 · Aug 31, 2017 · national
JP 2017-230388 · Nov 30, 2017 · national
JP 2018-029271 · Feb 22, 2018 · national
JP 2018-095317 · May 17, 2018 · national
Continuity (1)
Related Publication 20200194527A1 · Jun 18, 2020
Cited By (5)
US 12,217,699 US 12,347,386 US 12,586,539 US 12,586,540 US 12,720,915