Display apparatus
A display apparatus includes a pixel part including a plurality of pixels, and a gate driving circuit. Each of the plurality of pixels is driven in one first scan period and one or more second scan periods during one frame in a driving mode driven at a first driving frequency lower than a maximum driving frequency.
1 . A pixel comprising:
a first transistor;
a second transistor connected between a gate of the first transistor and a data line, a gate of the second transistor being connected to a first scan line;
a third transistor connected between the gate of the first transistor and a first voltage line, a gate of the third transistor being connected to a second scan line;
a fourth transistor connected between a second terminal of the first transistor and a second voltage line, a gate of the fourth transistor being connected to a third scan line;
a fifth transistor connected between a first terminal of the first transistor and a third voltage line, a gate of the fifth transistor being connected to a control line;
a first capacitor connected between the gate of the first transistor and the second terminal of the first transistor;
a second capacitor connected between the third voltage line and the second terminal of the first transistor; and
a light-emitting diode comprising an anode connected to the second terminal of the first transistor.
2 . The pixel of claim 1 , wherein
the pixel is driven in one first scan period and at least one second scan period during one frame in a driving mode driven at a first driving frequency lower than a maximum driving frequency,
a third second scan signal is supplied to the third scan line and a control signal is supplied to the control line according to the maximum driving frequency, and
a first scan signal is supplied to the first scan line and a second scan signal is supplied to the second scan line according to the first driving frequency.
3 . The pixel of claim 2 , wherein in case that the first driving frequency is 1/n of the maximum driving frequency,
each of a number of the first scan signal supplied to the first scan line and a number of the second scan signal supplied to the second scan line is 1,
each of a number of the third second scan signal supplied to the third scan line and a number of the control signal supplied to the control line is n, and
n is a natural number.
4 . The pixel of claim 2 , wherein a timing in which the third scan signal is supplied to the pixel in the first scan period and a timing in which the third scan signal is supplied to the pixel in the second scan period are substantially identical to each other.
5 . The pixel of claim 2 , wherein
the first scan period comprises a first non-light-emitting period and a first light-emitting period, and
each of the at least one second scan period comprises a second non-light-emitting period and a second light-emitting period,
the third scan signal is supplied to the third scan line before and after the first scan signal is supplied to the first scan line in the first non-light-emitting period of the first scan period,
the third scan signal is supplied to the third scan line twice in the second non-light-emitting period of the second scan period, and
a timing in which the third scan signal is supplied to the pixel in the first scan period and a timing in which the third scan signal is supplied to the pixel in the second scan period are substantially identical to each other.
6 . The pixel of claim 5 , wherein
the first scan period comprises:
a first period in which the second scan signal and the third scan signal each have a gate-on voltage level, and the first scan signal and the control signal each have a gate-off voltage level;
a second period in which the first scan signal and the third scan signal each have a gate-off voltage level, and the second scan signal and the control signal each have a gate-on voltage level;
a third period in which the first scan signal has a gate-on voltage level, and the second scan signal, the third scan signal, and the control signal each have a gate-off voltage level; and
a fourth period in which the first scan signal, the second scan signal, and the third scan signal each have a gate-off voltage level, and the control signal has a gate-on voltage level,
the fourth period is the first light-emitting period,
the at least one second scan period comprises a fifth period in the second non-light-emitting period, and
in the fifth period, the second scan signal has a gate-on voltage level and the first scan signal, the third scan signal, and the control signal each have a gate-off voltage level.
7 . The pixel of claim 6 , wherein
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the first scan period, and
the control signal is shifted from the gate-off voltage level to the gate-on voltage level once in the second scan period.
8 . The pixel of claim 6 , wherein
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the first scan period, and
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the second scan period.
9 . The pixel of claim 6 , wherein
the first scan period further comprises, between third period and the fourth period, a sixth period in which the first scan signal, the second scan signal, and the control signal each have the gate-off voltage level, and the third scan signal has the gate-on voltage level, and
the at least one second scan period further comprises, subsequent to the fifth period before the control signal is shifted from the gate-off voltage level to the gate-on voltage level, a seventh period in which the third scan signal has the gate-on voltage level.
10 . The pixel of claim 9 , wherein
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the first scan period, and
the control signal is shifted from the gate-off voltage level to the gate-on voltage level once in the second scan period.
11 . The pixel of claim 9 , wherein
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the first scan period, and
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the second scan period.
12 . The pixel of claim 6 , wherein the pixel further comprises a third capacitor connected between the anode and a fourth voltage line.
13 . The pixel of claim 12 , wherein a voltage supplied to the fourth voltage line is a voltage supplied to a cathode of the light-emitting diode or a voltage greater than a voltage supplied to the second voltage line.
14 . The pixel of claim 12 , wherein
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the first scan period, and
the control signal is shifted from the gate-off voltage level to the gate-on voltage level once in the second scan period.
15 . The pixel of claim 12 , wherein
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the first scan period, and
the control signal is shifted from the gate-off voltage level to the gate-on voltage level twice in the second scan period.
16 . The pixel of claim 12 , wherein
the first scan period further comprises, between the third period and the fourth period, a sixth period in which the first scan signal, the second scan signal, and the control signal each have the gate-off voltage level, and the third scan signal has the gate-on voltage level, and
the at least one second scan period further comprises, subsequent to the fifth period before the control signal is shifted from the gate-off voltage level to the gate-on voltage level, a seventh period in which the third scan signal has the gate-on voltage level.
17 . The pixel of claim 16 , wherein
a fourth voltage of a low level is supplied to the fourth voltage line from before a start of the first period to after the sixth period in the first scan period,
the fourth voltage of a low level is supplied to the fourth voltage line from before a start of the fifth period to after the seventh period in the at least one second scan period, and
the fourth voltage of a high level is supplied to the fourth voltage line during the first light-emitting period and the second light-emitting period.
18 . The pixel claim 16 , wherein a timing in which the third scan signal is supplied to the pixel in the first scan period and a timing in which the third scan signal is supplied to the pixel in the second scan period are substantially identical to each other.
19 . The pixel of claim 1 , wherein each of the first transistor to the fifth transistor is an N-channel oxide semiconductor transistor.
20 . A display apparatus comprising:
a display panel in which a plurality of pixels are arranged; and
a driving circuit providing signals to the plurality of pixels,
wherein each of the plurality of pixels comprises:
a first transistor;
a second transistor connected between a gate of the first transistor and a data line, a gate of the second transistor being connected to a first scan line;
a third transistor connected between the gate of the first transistor and a first voltage line, a gate of the third transistor being connected to a second scan line;
a fourth transistor connected between a second terminal of the first transistor and a second voltage line, a gate of the fourth transistor being connected to a third scan line;
a fifth transistor connected between a first terminal of the first transistor and a third voltage line, a gate of the fifth transistor being connected to a control line;
a first capacitor connected between the gate of the first transistor and the second terminal of the first transistor;
a second capacitor connected between the third voltage line and the second terminal of the first transistor; and
a light-emitting diode comprising an anode connected to the second terminal of the first transistor.
21 . The display apparatus of claim 20 , wherein
each of the plurality of pixels further comprises a third capacitor connected between the anode and a fourth voltage line, and
a voltage supplied to the fourth voltage line is a voltage supplied to a cathode of the light-emitting diode or a voltage greater than a voltage supplied to the second voltage line.
22 . The display apparatus of claim 20 , wherein
each of the plurality of pixels is driven in one first scan period and at least one second scan period during one frame in a driving mode driven at a first driving frequency lower than a maximum driving frequency,
the first scan period comprises a first non-light-emitting period and a first light-emitting period, and each of the at least one second scan period comprises a second non-light-emitting period and a second light-emitting period,
the first scan period comprises:
a first period in which the second scan signal and the third scan signal each have a gate-on voltage level, and the first scan signal and the control signal each have a gate-off voltage level;
a second period in which the first scan signal and the third scan signal each have a gate-off voltage level, and the second scan signal and the control signal each have a gate-on voltage level;
a third period in which the first scan signal has a gate-on voltage level, and the second scan signal, the third scan signal, and the control signal each have a gate-off voltage level; and
a fourth period in which the first scan signal, the second scan signal, and the third scan signal each have a gate-off voltage level, and the control signal has a gate-on voltage level,
the fourth period is the first light-emitting period,
the at least one second scan period comprises a fifth period in the second non-light-emitting period, and
in the fifth period, the second scan signal has a gate-on voltage level and the first scan signal, the third scan signal, and the control signal each have a gate-off voltage level.
23 . The display apparatus of claim 20 comprises one of a smartphone, a tablet personal computer, a laptop, a television and a billboard.