IP Library Granted Patent US 11,074,962
Granted Patent B2
US 11,074,962 · App. 16/640,206 · Granted Jul 27, 2021

Semiconductor device, memory device, and electronic device

Inventors: Tatsuya Onuki (Kanagawa, JP); Takanori Matsuzaki (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C11/4091G11C5/02G11C5/063H01L27/10805
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Quick Facts
Patent No.
US 11,074,962
App. No.
16/640,206
Granted
Jul 27, 2021
Kind
B2
Abstract

A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

Claims (21)

1. A memory device comprising:

a bit line;

a sense amplifier electrically connected to the bit line;

an input/output circuit stacked below the sense amplifier; and

a memory cell array stacked over the sense amplifier,

wherein the memory cell array includes a memory cell electrically connected to the bit line,

wherein the memory cell includes a write transistor electrically connected to the bit line and a capacitor electrically connected to the write transistor, and

wherein the bit line is not provided over the write transistor.

2. The memory device according to claim 1 , wherein a semiconductor layer of the write transistor includes a metal oxide.

3. An electronic device comprising the memory device according to claim 1 .

4. A memory device comprising:

a sense amplifier block including a bit line and a sense amplifier electrically connected to the bit line;

an input/output circuit stacked below the sense amplifier; and

a memory cell array stacked over the sense amplifier block,

wherein the memory cell array includes a conductor and a memory cell,

wherein the memory cell includes:

a write transistor electrically connected to the bit line through the conductor; and

a capacitor electrically connected to the write transistor, and

wherein the conductor includes a portion in contact with a bottom surface of a semiconductor layer of the write transistor.

5. The memory device according to claim 4 , wherein the semiconductor layer of the write transistor includes a metal oxide.

6. An electronic device comprising the memory device according to claim 4 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2020
From: ONUKI, TATSUYA; MATSUZAKI, TAKANORI; KATO, KIYOSHI; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 051863/0763 →
Priority Claims (2)
JP JP2017-170814 · Sep 6, 2017 · national
JP JP2018-034610 · Feb 28, 2018 · national
Continuity (1)
Related Publication 20200185023A1 · Jun 11, 2020
Cited By (2)
US 12,205,892 US 12,531,114