IP Library Granted Patent US 12,205,892
Granted Patent B2
US 12,205,892 · App. 17/297,863 · Granted Jan 21, 2025

Semiconductor device

Inventors: Akio Suzuki (Kanagawa, JP); Atsushi Miyaguchi (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L23/528H01L23/3107H01L23/3672H01L29/78648H01L29/7869
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Quick Facts
Patent No.
US 12,205,892
App. No.
17/297,863
Granted
Jan 21, 2025
Kind
B2
Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes a silicon substrate and a device provided above the silicon substrate. The device includes a transistor and a conductor. The transistor includes a metal oxide in a channel formation region. Conductivity is imparted to the silicon substrate. The conductor is electrically connected to each of a drain of the transistor and the silicon substrate through an opening provided in the device. Heat of the drain of the transistor can be efficiently released through the silicon substrate.

Claims (38)

1. A semiconductor device comprising:

a silicon substrate without a transistor; and

a device provided above the silicon substrate,

wherein the device comprises a transistor and a first conductor,

wherein the transistor comprises a metal oxide in a channel formation region,

wherein conductivity is imparted to the silicon substrate,

wherein the first conductor is electrically connected to each of a drain of the transistor and the silicon substrate through openings provided in the device, and

wherein the first conductor is in contact with a top surface of the silicon substrate.

2. The semiconductor device according to claim 1 ,

wherein p-type conductivity is imparted to the silicon substrate.

3. The semiconductor device according to claim 1 ,

wherein the silicon substrate and the device are covered with a resin layer, and

wherein the resin layer is provided in a housing.

4. The semiconductor device according to claim 1 ,

wherein the silicon substrate is provided with a heat sink with an insulating layer therebetween.

5. A semiconductor device comprising:

a silicon substrate without a transistor;

a device provided above the silicon substrate;

a first extraction electrode; and

a second extraction electrode,

wherein the device comprises a transistor and a first conductor,

wherein the transistor comprises a metal oxide in a channel formation region,

wherein conductivity is imparted to the silicon substrate,

wherein the first conductor is electrically connected to each of a drain of the transistor and the silicon substrate through openings provided in the device,

wherein the first conductor is in contact with a top surface of the silicon substrate,

wherein the first extraction electrode is electrically connected to a second conductor connected to a source of the transistor, and

wherein the second extraction electrode is electrically connected to the silicon substrate.

6. The semiconductor device according to claim 5 ,

wherein the first extraction electrode is electrically connected to, through a metal wiring, the second conductor.

7. The semiconductor device according to claim 5 ,

wherein the second extraction electrode is directly connected to the silicon substrate.

8. The semiconductor device according to claim 5 ,

wherein p-type conductivity is imparted to the silicon substrate.

9. The semiconductor device according to claim 5 ,

wherein the silicon substrate and the device are covered with a resin layer, and

wherein the resin layer is provided in a housing.

10. The semiconductor device according to claim 5 ,

wherein the silicon substrate is provided with a heat sink with an insulating layer therebetween.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2021
From: SUZUKI, AKIO; MIYAGUCHI, ATSUSHI; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 056376/0495 →
Priority Claims (1)
JP 2018-243859 · Dec 27, 2018 · national
Continuity (1)
Related Publication 20220020683A1 · Jan 20, 2022
References Cited (56)
US 6121659A · Christensen et al. · 2000 [cited by applicant]
US 7378747B2 · Kim · 2008 [cited by applicant]
US 8421068B2 · Yamazaki et al. · 2013 [cited by applicant]
US 8803206B1 · Or-Bach et al. · 2014 [cited by applicant]
US 9281237B2 · Yamazaki · 2016 [cited by applicant]
US 9385058B1 · Or-Bach et al. · 2016 [cited by applicant]
US 9460978B1 · Or-Bach et al. · 2016 [cited by applicant]
US 9460991B1 · Or-Bach et al. · 2016 [cited by applicant]
US 9553202B2 · Kurata et al. · 2017 [cited by applicant]
US 9666678B2 · Yamazaki et al. · 2017 [cited by applicant]
US 9674470B2 · Kurokawa et al. · 2017 [cited by applicant]
US 9685500B2 · Yamazaki et al. · 2017 [cited by applicant]
US 9911627B1 · Or-Bach et al. · 2018 [cited by applicant]
US 9917207B2 · Yamazaki · 2018 [cited by applicant]
US 9923001B2 · Yamazaki · 2018 [cited by applicant]
US 9929276B2 · Yamazaki · 2018 [cited by applicant]
US 9947700B2 · Yamazaki et al. · 2018 [cited by applicant]
US 10020336B2 · Ikeda et al. · 2018 [cited by applicant]
US 10074747B2 · Yamazaki et al. · 2018 [cited by applicant]
US 10236357B2 · Yamane et al. · 2019 [cited by applicant]
US 10333004B2 · Kimura et al. · 2019 [cited by applicant]
US 10522688B2 · Kato et al. · 2019 [cited by applicant]
US 10658389B2 · Kurata et al. · 2020 [cited by applicant]
US 10777682B2 · Yamazaki et al. · 2020 [cited by applicant]
US 11031506B2 · Yamazaki et al. · 2021 [cited by applicant]
US 11074962B2 · Onuki et al. · 2021 [cited by applicant]
US 11837461B2 · Yamazaki et al. · 2023 [cited by applicant]
US 20060255468A1 · Kim · 2006 [cited by applicant]
US 20110057254A1 · Tsen et al. · 2011 [cited by applicant]
US 20110254523A1 · Ito et al. · 2011 [cited by applicant]
US 20140102877A1 · Yamazaki · 2014 [cited by applicant]
US 20150255367A1 · Nakahara · 2015 [cited by examiner]
US 20150349127A1 · Kurata · 2015 [cited by examiner]
US 20170098599A1 · Zhou · 2017 [cited by examiner]
US 20200321360A1 · Kurata et al. · 2020 [cited by applicant]
US 20210126130A1 · Yamazaki et al. · 2021 [cited by applicant]
US 20210233769A1 · Yamazaki et al. · 2021 [cited by applicant]
CN 001862796A · 2006 [cited by applicant]
EP 0948054A · 1999 [cited by applicant]
JP 11330489A · 1999 [cited by applicant]
JP 2006319338A · 2006 [cited by applicant]
JP 2011103458A · 2011 [cited by applicant]
JP 2013089613A · 2013 [cited by applicant]
JP 2016006855A · 2016 [cited by applicant]
JP 2016162913A · 2016 [cited by applicant]
KR 100644028 · 2006 [cited by applicant]
KR 20170015292A · 2017 [cited by applicant]
TW 200644207 · 2006 [cited by applicant]
TW 201545351 · 2015 [cited by applicant]
WO WO2011046048 · 2011 [cited by applicant]
WO WO2015182000 · 2015 [cited by applicant]
WO WO2017125795 · 2017 [cited by applicant]
International Search Report (Application No. PCT/IB2019/059960) Dated Feb. 18, 2020. [cited by applicant]
Written Opinion (Application No. PCT/IB2019/059960) Dated Feb. 18, 2020. [cited by applicant]
Kunitake.H et al., “High thermal tolerance of 25-nm c-axis aligned crystalline In—Ga—Zn oxide FET”, IEDM 18: Technical Digest of International Electron Devices Meeting, Dec. 1, 2018, pp. 312-315. [cited by applicant]
Takahashi.T et al., “Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and Ultra-Thin BOX SOI MOSFETs: Impacts of Doped Well, Ambient Temperature, and SOI/BOX Thicknesses on SHE”, IEDM 13: Technical Digest o… [cited by applicant]