IP Library › Granted Patent US 11,837,461
Granted Patent B2
US 11,837,461 · App. 17/010,151 · Granted Dec 5, 2023

Semiconductor device and manufacturing method thereof

Inventors: Shunpei Yamazaki (Tokyo, JP); Jun Koyama (Kanagawa, JP); Hiroyuki Miyake (Kanagawa, JP); Kei Takahashi (Kanagawa, JP); Kouhei Toyotaka (Kanagawa, JP); Masashi Tsubuku (Kanagawa, JP); Kosei Noda (Kanagawa, JP); Hideaki Kuwabara (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/78609G06K19/07758H01L21/8236H01L23/66H01L27/0883H01L27/1225H01L29/24H01L29/26H01L29/66969H01L29/7869H01L29/78696G11C7/00G11C19/28H01L2223/6677H02M3/07
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Quick Facts
Patent No.
US 11,837,461
App. No.
17/010,151
Granted
Dec 5, 2023
Kind
B2
Abstract

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

Claims (27)

1. A semiconductor device comprising:

a first transistor over a glass substrate, the first transistor comprising a first oxide semiconductor layer where a channel formation region is provided,

a second transistor over the glass substrate, the second transistor comprising a second oxide semiconductor layer where a channel formation region is provided,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium and zinc,

wherein a conductive layer is provided between the substrate and the first oxide semiconductor layer,

wherein a first insulating layer is provided between the conductive layer and the first oxide semiconductor layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer are over and in direct contact with the first insulating layer,

wherein a channel length of the first transistor is longer than a channel length of the second transistor,

wherein no conductive layer is provided between the substrate and the second oxide semiconductor layer, and

wherein a size of crystal grains in each of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 1 nm and smaller than or equal to 20 nm.

2. The semiconductor device according to claim 1 , wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×10 19 /cm 3 .

3. The semiconductor device according to claim 1 , wherein an off-current of each of the first transistor and the second transistor is less than or equal to 1×10 −13 A.

4. A semiconductor device comprising:

a first transistor over a glass substrate, the first transistor comprising a first oxide semiconductor layer where a channel formation region is provided,

a second transistor over the glass substrate, the second transistor comprising a second oxide semiconductor layer where a channel formation region is provided,

wherein the first transistor comprises a first conductive layer and a second conductive layer,

wherein each of the first conductive layer and a second conductive layer are over the first oxide semiconductor layer,

wherein the second transistor comprises a third conductive layer and a fourth conductive layer,

wherein each of the third conductive layer and the fourth conductive layer are over the second oxide semiconductor layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium and zinc,

wherein a conductive layer is provided between the substrate and the first oxide semiconductor layer,

wherein a first insulating layer is provided between the conductive layer and the first oxide semiconductor layer,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer are over and in direct contact with the first insulating layer,

wherein a channel length of the first transistor is longer than a channel length of the second transistor, and

wherein a size of crystal grains in each of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 1 nm and smaller than or equal to 20 nm.

5. The semiconductor device according to claim 4 , wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×10 19 /cm 3 .

6. The semiconductor device according to claim 4 , wherein an off-current of each of the first transistor and the second transistor is less than or equal to 1×10 −13 A.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2020
From: YAMAZAKI, SHUNPEI; KOYAMA, JUN; MIYAKE, HIROYUKI; TAKAHASHI, KEI; TOYOTAKA, KOUHEI; TSUBUKU, MASASHI; NODA, KOSEI; KUWABARA, HIDEAKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 053676/0100 →
Priority Claims (1)
JP 2009-238885 · Oct 16, 2009 · national
Continuity (5)
Continuation 16121700 · Sep 5, 2018
Continuation 15372493 · Dec 8, 2016
Division 13799246 · Mar 13, 2013
Continuation 12904565 · Oct 14, 2010
Related Publication 20210143281A1 · May 13, 2021
Cited By (1)
US 12,205,892