IP Library Granted Patent US 10,522,688
Granted Patent B2
US 10,522,688 · App. 15/380,502 · Granted Dec 31, 2019

Semiconductor device including transistor which includes first gate and second gate

Inventors: Kiyoshi Kato (Kanagawa, JP); Tomoaki Atsumi (Kanagawa, JP); Shunpei Yamazaki (Takyo, JP); Haruyuki Baba (Kanagawa, JP); Shinpei Matsuda (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L27/088H01L27/108H01L27/124H01L27/1225H01L27/1255H01L29/78648H01L29/78696
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,522,688
App. No.
15/380,502
Granted
Dec 31, 2019
Kind
B2
Abstract

A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.

Claims (54)

1. A semiconductor device comprising:

a first transistor comprising a first gate, a second gate, and a first oxide semiconductor in a channel formation region;

a second transistor comprising a third gate, a fourth gate, and a second oxide semiconductor in a channel formation region; and

a circuit configured to generate a negative potential,

wherein the first gate of the first transistor and the second gate of the first transistor overlap with each other in a region with the first oxide semiconductor of the first transistor between the first gate of the first transistor and the second gate of the first transistor,

wherein the third gate of the second transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the one of the source and the drain of the second transistor is electrically connected to the second gate of the first transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the circuit,

wherein the fourth gate of the second transistor is electrically connected to the third gate of the second transistor,

wherein each of the first oxide semiconductor of the first transistor and the second oxide semiconductor of the second transistor comprises In and Ga, and

wherein a bandgap of the second oxide semiconductor of the second transistor is wider than a bandgap of the first oxide semiconductor of the first transistor.

2. The semiconductor device according to claim 1 , wherein a ratio of a number of Ga atoms to a number of In atoms in the second oxide semiconductor of the second transistor is higher than a ratio of a number of Ga atoms to a number of In atoms in the first oxide semiconductor of the first transistor.

3. A memory device comprising the semiconductor device according to claim 1 .

4. An electronic device comprising:

the semiconductor device according to claim 1 ; and

a display device, a microphone, a speaker, an operation key, or a housing.

5. A semiconductor device comprising:

a first transistor comprising a first gate, a second gate, and a first oxide semiconductor in a channel formation region;

a second transistor comprising a third gate, a fourth gate, and a second oxide semiconductor in a channel formation region;

a third transistor;

a capacitor; and

a circuit configured to generate a negative potential,

wherein the first gate of the first transistor and the second gate of the first transistor overlap with each other in a region with the first oxide semiconductor of the first transistor between the first gate of the first transistor and the second gate of the first transistor,

wherein the third gate of the second transistor is electrically connected to a gate of the third transistor and a first terminal of the capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to the second gate of the first transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the circuit,

wherein the fourth gate of the second transistor is electrically connected to the third gate of the second transistor,

wherein each of the first oxide semiconductor of the first transistor and the second oxide semiconductor of the second transistor comprises In and Ga, and

wherein a bandgap of the second oxide semiconductor of the second transistor is wider than a bandgap of the first oxide semiconductor of the first transistor.

6. The semiconductor device according to claim 5 , wherein the bandgap of the second oxide semiconductor of the second transistor is greater than or equal to 2.2 eV.

7. The semiconductor device according to claim 5 , wherein a ratio of a number of Ga atoms to a number of In atoms in the second oxide semiconductor of the second transistor is higher than a ratio of a number of Ga atoms to a number of In atoms in the first oxide semiconductor of the first transistor.

8. A memory device comprising the semiconductor device according to claim 5 .

9. An electronic device comprising:

the semiconductor device according to claim 5 ; and

a display device, a microphone, a speaker, an operation key, or a housing.

10. The semiconductor device according to claim 1 , further comprising a capacitor,

wherein a first terminal of the capacitor is electrically connected to the one of the source and the drain of the second transistor.

11. A semiconductor device comprising:

a first transistor comprising a first gate, a second gate, and a first oxide semiconductor in a channel formation region;

a second transistor comprising a third gate, a fourth gate, and a second oxide semiconductor in a channel formation region; and

a circuit configured to generate a negative potential,

wherein the first gate of the first transistor and the second gate of the first transistor overlap with each other in a region with the first oxide semiconductor of the first transistor between the first gate of the first transistor and the second gate of the first transistor,

wherein the third gate of the second transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the one of the source and the drain of the second transistor is electrically connected to the second gate of the first transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the circuit,

wherein the fourth gate of the second transistor is electrically connected to the third gate of the second transistor, and

wherein each of the first oxide semiconductor of the first transistor and the second oxide semiconductor of the second transistor comprises In and Ga.

12. The semiconductor device according to claim 11 , wherein a ratio of a number of Ga atoms to a number of In atoms in the second oxide semiconductor of the second transistor is higher than a ratio of a number of Ga atoms to a number of In atoms in the first oxide semiconductor of the first transistor.

13. A memory device comprising the semiconductor device according to claim 11 .

14. An electronic device comprising:

the semiconductor device according to claim 11 ; and

a display device, a microphone, a speaker, an operation key, or a housing.

15. The semiconductor device according to claim 11 , further comprising a capacitor,

wherein a first terminal of the capacitor is electrically connected to the one of the source and the drain of the second transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2016
From: KATO, KIYOSHI; ATSUMI, TOMOAKI; YAMAZAKI, SHUNPEI; BABA, HARUYUKI; MATSUDA, SHINPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 040637/0183 →
Priority Claims (1)
JP 2015-247680 · Dec 18, 2015 · national
Continuity (1)
Related Publication 20170179294A1 · Jun 22, 2017
Cited By (1)
US 12,205,892