Low temperature bonded structures
Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second conductive interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
1. A microelectronic assembly, comprising:
a first substrate having a bonding surface, the bonding surface of the first substrate having a planarized topography;
a first plurality of metallic features at the bonding surface of the first substrate;
a first recessed portion disposed in a surface of one or more of the first plurality of metallic features and extending a preselected depth below the bonding surface of the first substrate, the first recessed portion at least partially filled with a first material different than a conductive material of the first plurality of metallic features;
a second substrate having a bonding surface, the bonding surface of the second substrate having a planarized topography and bonded to the bonding surface of the first substrate; and
a second plurality of metallic features at the bonding surface of the second substrate and bonded to the first plurality of metallic features, either or both of the first plurality of metallic features and the second plurality of metallic features comprising two or more materials, including at least one non-barrier conductive material or silicon-containing material provided over an underlying conductive material of the first or second plurality of metallic features.
2. The microelectronic assembly of claim 1 , further comprising a second recessed portion disposed in a surface of the second plurality of metallic features and extending a preselected depth below the bonding surface of the second substrate, the second recessed portion at least partially filled with a second material different than the conductive material of the second plurality of metallic features.
3. The microelectronic assembly of claim 2 , further comprising a barrier layer disposed within the first recessed portion and/or the second recessed portion, between the conductive material of the first plurality of metallic features and the first material and/or between the conductive material of the second plurality of metallic features and the second material, the barrier layer comprising a third conductive material different from the first or second materials and different than the conductive material of the first or second plurality of metallic features.
4. The microelectronic assembly of claim 2 , wherein the first and second materials combine to form a fill mass disposed between the first plurality of metallic features and the second plurality of metallic features.
5. The microelectronic assembly of claim 4 , wherein a melting point of the fill mass is higher than respective melting points of the first or second material.
6. The microelectronic assembly of claim 4 , wherein the fill mass comprises a polysilicon.
7. The microelectronic assembly of claim 1 , wherein the bonding surface of the second substrate is bonded to the bonding surface of the first substrate via direct bonding without adhesive.
8. A microelectronic assembly, comprising:
a first substrate having a surface and a first conductive structure comprising a first conductive feature and a first element;
a second substrate having a surface and a second conductive structure, the surface of the first substrate intimately bonded to the surface of the second substrate, and the first conductive structure bonded to the second conductive structure; and
a fill region coupling the first conductive structure to the second conductive structure, wherein the fill region includes the first element, the first element having a melting point higher than a melting point of the first conductive feature or portions of the second conductive structure.
9. The microelectronic assembly of claim 8 , wherein the fill region comprises cobalt, nickel, and/or manganese.
10. The microelectronic assembly of claim 8 , wherein the fill region comprises polysilicon.
11. The microelectronic assembly of claim 8 , wherein the fill region has a thickness that is thinner than a thickness of the first conductive structure or the second conductive structure.
12. A microelectronic assembly, comprising:
a first substrate having a surface and a first conductive structure comprising a first element;
a second substrate having a surface and a second conductive structure, the surface of the first substrate intimately bonded to the surface of the second substrate, and the first conductive structure bonded to the second conductive structure; and
a fill region comprising the first element coupling the first conductive structure to the second conductive structure, the first element including polysilicon, wherein the fill region is a discontinuous layer.
13. The microelectronic assembly of claim 12 , wherein the fill region has a thickness that is thinner than a thickness of the first conductive structure or the second conductive structure.
14. The microelectronic assembly of claim 12 , wherein the fill region has a thickness of less than 100 nm.
15. The microelectronic assembly of claim 12 , wherein the fill region has a thickness of less than 5 nm.
16. The microelectronic assembly of claim 12 , wherein the fill region separates the first conductive structure from the second conductive structure.
17. The microelectronic assembly of claim 12 , wherein the fill region partially separates the first conductive structure from the second conductive structure with portions of the first conductive structure contacting portions of the second conductive structure.
18. The microelectronic assembly of claim 12 , wherein the first conductive structure bonded to the second conductive structure contains one or more voids.
19. The microelectronic assembly of claim 12 , wherein a CTE of the fill region is smaller than a CTE of the first conductive structure or a CTE of the second conductive structure.
20. The microelectronic assembly of claim 12 , wherein a CTE of the fill region is similar to a CTE of the first substrate or the second substrate or silicon.
21. The microelectronic assembly of claim 12 , wherein the first element has a cross-sectional diameter less than the cross-sectional diameter of the first and second conductive structures, such that there is either a void around the perimeter of the fill region or the first and second conductive structures are in contact around the perimeter of the fill region.
22. The microelectronic assembly of claim 12 , wherein the lateral width of the fill region is larger than the lateral width of the first conductive structure or the lateral width of the second conductive structure or both.
23. The microelectronic assembly of claim 12 , wherein the first substrate has a plurality of first conductive structures of varying cross-sectional sizes, the second substrate has a plurality of second conductive structures of varying cross-sectional sizes, and an amount of a fill element in each of the first and second conductive structures varies based on the cross-sectional size of the respective first or second conductive structure.
24. A microelectronic assembly, comprising:
a first substrate having a surface and a first conductive structure comprising a first element;
a second substrate having a surface and a second conductive structure, the surface of the first substrate intimately bonded to the surface of the second substrate, and the first conductive structure bonded to the second conductive structure; and
a first fill region comprising the first element coupling the first conductive structure to the second conductive structure, wherein the first conductive structure bonded to the second conductive structure contains one or more voids.