IP Library Granted Patent US 10,924,552
Granted Patent B2
US 10,924,552 · App. 16/656,411 · Granted Feb 16, 2021

Hyper-converged flash array system

Inventor: Daisuke Hashimoto (Cupertino, CA)
Assignee: TOSHIBA MEMORY CORPORATION
H04L67/1097G06F3/061G06F3/0604G06F3/0659G06F3/0688G06F12/0246G06F3/067G06F3/0665G06F2212/1024G06F2212/7201
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,924,552
App. No.
16/656,411
Granted
Feb 16, 2021
Kind
B2
Abstract

A distributed system includes a plurality of storage systems and a network connecting the storage systems. Each storage system includes a host having a processor and a memory, and a storage device having a controller and a nonvolatile memory. When a first storage system receives, a second storage system, a write command, write data, and size information of the write data, the controller in the first storage system determines an address of the nonvolatile memory of the first storage system in which the write data are to be written, based on the write command and the size information, writes the write data in the nonvolatile memory associated with the address, and transmits the address to the second storage system, and the processor of the second storage system stores management data indicating correspondence between identification information of the write data and the address in the memory of the second storage system.

Claims (69)

1. A host device for a first storage system including a plurality of storage devices each including a nonvolatile semiconductor memory, the host device comprising:

an internal interface controller connectable to the plurality of storage devices;

an external network interface connectable to a plurality of storage systems including a second storage system through a storage system network;

a memory; and

a processor configured to:

upon receipt of an access command from the second storage system through the storage system network, temporarily store the access command in the memory, and

control the internal interface controller to transmit the access command to one of the storage devices so that said one of the storage devices accesses the nonvolatile semiconductor memory thereof in accordance with the access command,

wherein the access command is issued by an operating system executed by the second storage system, which works with an operating system executed by the first storage system in a coordinated manner.

2. The host device according to claim 1 , wherein

when the access command is a write command, upon receipt of write data from the second storage system through the storage system network, the processor temporarily stores the write data in the memory, and

the processor controls the internal interface controller to transmit the write data to said one of the storage devices so that said one of the storage devices writes the write data into the nonvolatile semiconductor memory thereof.

3. The host device according to claim 2 , wherein

the write command includes no address information relating to a location into which the write data are to be written, and

the processor controls the internal interface controller to transmit the write command to said one of the storage devices so that said one of the storage devices determines a physical location of the nonvolatile semiconductor memory thereof, into which the write data are to be written, and returns the determined physical location to the host device.

4. The host device according to claim 3 , wherein

upon receipt of the physical location returned from said one of the storage devices, the processor controls the external network interface to transmit the physical location to the second storage system through the storage system network.

5. The host device according to claim 1 , wherein

when the access command is a read command, the processor controls the internal interface controller to transmit the read command to said one of the storage devices so that said one of the storage devices reads data from a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the read command, and

the processor controls the external network interface to transmit the read data to the second storage system through the storage system network.

6. The host device according to claim 1 , wherein

when the access command is an invalidate command, the processor controls the internal interface controller to transmit the invalidate command to said one of the storage devices so that said one of the storage devices invalidates data stored in a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the invalidate command, and

upon completion of the invalidation, the processor controls the external network interface to return a completion notification to the second storage system through the storage system network.

7. The host device according to claim 1 , wherein

when the access command is a copy command, the processor controls the internal interface controller to transmit the copy command to said one of the storage devices so that said one of the storage devices reads data from a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the copy command, and

upon receipt of the read data, the processor controls the external network interface to transmit the read data to another storage system designated by the copy command, through the storage system network.

8. The host device according to claim 1 , wherein

the processor is further configured to:

generate an outbound access command, and

control the external network interface to transmit the outbound access command to another storage system through the storage system network.

9. The host device according to claim 8 , wherein

the memory stores mapping from an identification or a logical address of each data unit to a physical location in which said each data unit is stored, and

the mapping includes mapping information for data stored in a nonvolatile semiconductor memory of said another storage system.

10. The host device according to claim 9 , wherein

the processor is further configured to:

determine a physical location in said another storage system to be accessed, by referring to the mapping when generating a read command, an invalidate command, or a copy command as the outbound access command, and

not determine the physical location when generating a write command as the outbound access command.

11. A method of operating a host device in a first storage system, the method comprising:

upon receipt of an access command from a second storage system through a storage system network, temporarily storing the access command in a memory of the host device; and

transmitting the access command to one of a plurality of storage devices connected to the host device so that said one of the storage devices accesses a nonvolatile semiconductor memory thereof in accordance with the access command,

wherein the access command is issued by an operating system executed by the second storage system, which works with an operating system executed by the first storage system in a coordinated manner.

12. The method according to claim 11 , further comprising:

when the access command is a write command, upon receipt of write data from the second storage system through the storage system network, temporarily storing the write data in the memory; and

transmitting the write data to said one of the storage devices so that said one of the storage devices writes the write data into the nonvolatile semiconductor memory thereof.

13. The method according to claim 12 , wherein

the write command includes no address information relating to a location into which the write data are to be written, and

the write command causes said one of the storage devices to determine a physical location of the nonvolatile semiconductor memory thereof, into which the write data are to be written, and return the determined physical location to the host device.

14. The method according to claim 13 , further comprising:

upon receipt of the physical location returned from said one of the storage devices, transmitting the physical location to the second storage system through the storage system network.

15. The method according to claim 11 , wherein

the access command is a read command that causes said one of the storage devices to read data from a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the read command, and

the method further comprises:

upon receipt of the read data from said one of the storage devices, transmitting the read data to the second storage system through the storage system network.

16. The method according to claim 11 , wherein

the access command is an invalidate command that causes said one of the storage devices to invalidate data stored in a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the invalidate command, and

the method further comprises:

upon completion of the invalidation, returning a completion notification to the second storage system through the external network interface.

17. The method according to claim 11 , wherein

the access command is a copy command that causes said one of the storage devices to read data from a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the copy command, and

the method further comprises:

upon receipt of the read data from said one of the storage devices, transmitting the read data to another storage system designated by the copy command, through the storage system network.

18. The method according to claim 11 , further comprising:

generating an outbound access command; and

transmitting the outbound access command to another storage system through the storage system network.

19. The method according to claim 18 , further comprising:

storing, in the memory, mapping from an identification or a logical address of each data unit to a physical location in which said each data unit is stored, wherein

the mapping includes mapping information for data stored in a nonvolatile semiconductor memory of said another storage system connected to the storage system network.

20. The method according to claim 19 , further comprising:

determining a physical location in said another storage system to be accessed, by referring to the mapping when generating a read command, an invalidate command, or a copy command as the outbound access command, wherein

the physical location is not determined when a write command is generated as the outbound access command.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
Continuity (3)
Continuation 15253679 · Aug 31, 2016
Provisional Application 62268366 · Dec 16, 2015
Related Publication 20200053154A1 · Feb 13, 2020