Display driver semiconductor device and manufacturing method thereof

1. A semiconductor device, comprising:

an isolating region and drift regions formed in a substrate,

a source region and a drain region formed in the drift regions;

a gate insulating layer formed on the substrate;

a gate electrode on the gate insulating layer;

spacers formed on side walls of the gate electrode;

a silicide layer selectively formed on a portion of the drain region and a portion of the gate electrode;

a silicide blocking insulating layer selectively formed on a remaining portion of the drain region and a remaining portion of the gate electrode; and

wherein the silicide layer formed on the portion of the drain region has a length smaller than a length of the drain region, and the silicide layer overlapping one of the drift regions has a length smaller than a length of the silicide blocking insulating layer overlapping the one of the drift regions.

2. The semiconductor device of claim 1 , wherein the source region and the drain region are formed at a predetermined distance from the spacers.

3. The semiconductor device of claim 1 , wherein the silicide layer formed on the portion of the gate electrode has a length smaller than a length of the gate electrode.

4. The semiconductor device of claim 1 , wherein the silicide layer abuts the isolating region.

5. The semiconductor device of claim 1 , wherein the silicide layer is a nickel silicide (NiSi) layer or a cobalt silicide (CoSi 2 ) layer.

6. The semiconductor device of claim 1 , wherein the isolating region has a maximum depth larger than a maximum depth of the drift regions which is larger than a maximum depth of the source region or the drain region, the respective maximum depths being measured from an upper surface of the substrate.

7. The semiconductor device of claim 1 , wherein an edge portion of the gate electrode has a height greater than a height of a central portion of the gate electrode.

8. The semiconductor device of claim 1 , wherein the silicide blocking insulating layer is formed over one of the side walls.

9. The semiconductor device of claim 1 , further comprising a first insulating layer formed on the silicide blocking insulating layer.

10. The semiconductor device of claim 9 , further comprising:

an interlayer insulating layer formed on the first insulating layer; and

a contact plug formed in the interlayer insulating layer and the first insulating layer.

11. A semiconductor device, comprising:

a first gate insulating layer and a second gate insulating layer formed on a substrate;

a first gate electrode and a second gate electrode respectively formed on the first gate insulating layer and the second gate insulating layer;

spacers formed on side walls of the first gate electrode and the second gate electrode;

a first drain region disposed adjacent to the first gate electrode;

a second drain region disposed adjacent to the second gate electrode;

a first drift region surrounding the first drain region;

a second drift region surrounding the second drain region;

a common source region formed between the first gate electrode and the second gate electrode;

a silicide layer partially formed on a portion of the first drain region and a portion of the second drain region; and

a silicide blocking insulating layer partially formed on a remaining portion of the first drain region and a remaining portion of the second drain region.

12. The semiconductor device of claim 11 , further comprising:

a third drift region surrounding the common source region.

13. The semiconductor device of claim 11 , wherein the silicide layer entirely formed on the common source region.

14. The semiconductor device of claim 11 , wherein the silicide layer has a length smaller than a length of the first drain region or the second drain region, respectively.

15. The semiconductor device of claim 12 , wherein the silicide layer overlapping the first drift region has a length smaller than a length of the silicide blocking insulating layer overlapping the first drift region.

16. The semiconductor device of claim 11 , wherein the source region and the drain region are formed at a predetermined distance from the spacers.

17. A method for manufacturing a semiconductor device, the method comprising:

forming a well region on a substrate;

forming drift regions in the well region;

forming a gate insulating layer overlapping the drift regions;

forming a gate electrode on the gate insulating layer;

forming spacers on side walls of the gate electrode;

forming a first photoresist pattern on the drift regions and the gate electrode, wherein the drift regions and the gate electrode are partially exposed;

implanting dopant ions into the exposed drift regions and the exposed gate electrode using the first photo mask pattern to form a source region and a drain region in the drift regions;

removing the first photoresist pattern;

forming a protection insulating layer on the substrate;

forming a second photoresist pattern on the drift regions and the gate electrode, wherein the drift regions and the gate electrode are partially exposed;

etching the protection insulating layer using the second photoresist pattern as a mask to partially expose a portion of the drain region and a portion of the gate electrode;

removing the second photoresist pattern;

forming a silicide layer on the portion of the drain region and the portion of the gate electrode, while the protection insulating layer remains on a remaining portion of the drain region and a remaining portion of the gate electrode;

forming a first insulating layer on the protection insulating layer and the gate electrode;

forming a second insulating layer on the first insulating layer; and

forming a contact plug in the first insulating layer and the second insulating layer,

wherein the silicide layer formed on the portion of the drain region has a length smaller than a length of the drain region, and

wherein the silicide layer overlapping one of the drift regions has a length smaller than a length of the protection insulating layer overlapping the one of the drift regions.

18. The method of claim 17 , wherein the first photo mask pattern partially overlaps the drift region and the gate electrode.

19. The method of claim 17 , wherein the second photo mask pattern overlaps the gate electrode more than the first photo mask pattern.