Semiconductor wafer manufacturing method and semiconductor device

1. A semiconductor wafer manufacturing method comprising:

forming a plurality of trench capacitors at a main surface of a semiconductor wafer,

wherein each of the plurality of trench capacitors is configured as unit cells that internally include unit trench capacitors, and

wherein a length component in a predetermined direction of a layout pattern of trenches of the plurality of trench capacitors is made equivalent, within a fixed tolerance range, to a length component in a direction that intersects the predetermined direction,

wherein each unit cell includes a first trench including a slit that divides a length of the first trench to be within a predetermined upper-limit value, and a second trench including a slit that divides a length of the second trench to be within the predetermined upper-limit value, the second trench disposed adjacent to the first trench at an inner side of the first trench with respect to a center of the unit cell with a space between the first and second trenches.

2. The semiconductor wafer manufacturing method according to claim 1 , wherein:

the length component in the predetermined direction of the layout pattern of the trenches of the plurality of trench capacitors is made different from the length component in the direction that intersects the predetermined direction, and

by disposing each of the plurality of unit cells after rotating relatively to each other, the length component in the predetermined direction of the layout pattern of the trenches of the plurality of trench capacitors is made equivalent, within the fixed tolerance range, to the length component in the direction that intersects the predetermined direction.

3. The semiconductor wafer manufacturing method according to claim 2 , wherein the layout pattern of the trenches in a layout pattern of the unit trench capacitors includes the slits that are used to limit the length of the trenches to not more than the predetermined upper-limit value.

4. The semiconductor wafer manufacturing method according to claim 3 , wherein the layout pattern of the trenches in the layout pattern of the unit trench capacitors is formed by combining unit patterns in which a plurality of line segments that include line segments extending in at least two different directions are connected together.

5. The semiconductor wafer manufacturing method according to claim 1 , wherein the length component in the predetermined direction of the layout pattern of the trenches of the plurality of trench capacitors is made equivalent, within the fixed tolerance range, to the length component in the direction that intersects the predetermined direction as a result of the length component in the predetermined direction of the layout pattern of the trenches of the unit trench capacitors being made equivalent, within the fixed tolerance range, to the length component in the direction that intersects the predetermined direction.

6. The semiconductor wafer manufacturing method according to claim 2 , wherein an outer shape of the unit cells is formed as a regular polygonal shape, and the unit cells are laid within a plane such that there are no gaps between adjacent unit cells of the unit cells.

7. The semiconductor wafer manufacturing method according to claim 2 , wherein the layout patterns of the trenches of the unit trench capacitors of each of the plurality of unit cells are mutually independent.

8. The semiconductor wafer manufacturing method according to claim 1 , wherein the layout patterns of the trenches of the unit trench capacitors of each of the plurality of unit cells are in mutual contact with each other.

9. The semiconductor wafer manufacturing method according to claim 2 , wherein each of the unit trench capacitors includes plural trench capacitors from among the plurality of trench capacitors.