Semiconductor device comprising oxide semiconductor layer containing a c-axis aligned crystal
View Patent ↗A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.
1. A semiconductor device comprising:
a first gate electrode layer;
a first insulating layer over the first gate electrode layer;
an oxide semiconductor layer comprising In, Ga, and Zn over the first insulating layer;
a source electrode layer and a drain electrode layer each electrically connected to the oxide semiconductor layer;
a second insulating layer over the oxide semiconductor layer; and
a second gate electrode layer over the second insulating layer,
wherein the oxide semiconductor layer comprises a channel formation region of a transistor,
wherein the oxide semiconductor layer comprises a region overlapping with each of the first gate electrode layer, the second gate electrode layer and one of the source electrode layer and the drain electrode layer,
wherein the region comprises a crystal region containing a c-axis aligned crystal, and
wherein in a channel length direction the width of the oxide semiconductor layer is larger than the width of the second gate electrode layer.
2. The semiconductor device according to claim 1 ,
wherein the semiconductor device is configured to apply to the first gate electrode layer a voltage that can be different from a voltage applied to the second gate electrode layer.
3. The semiconductor device according to claim 1 , further comprising a third insulating layer over the second gate electrode layer and a fourth insulating layer over the third insulating layer.
4. The semiconductor device according to claim 1 , wherein the crystal region includes a part of the top surface of the oxide semiconductor layer.
5. A semiconductor device comprising:
a first gate electrode layer;
a first insulating layer over the first gate electrode layer;
an oxide semiconductor layer comprising In, Ga, and Zn over the first insulating layer;
a source electrode layer and a drain electrode layer each electrically connected to the oxide semiconductor layer;
a second insulating layer over the oxide semiconductor layer; and
a second gate electrode layer over the second insulating layer,
wherein the oxide semiconductor layer comprises a channel formation region of a transistor,
wherein the oxide semiconductor layer overlaps in a first region with each of the first gate electrode layer, the second gate electrode layer and one of the source electrode layer and the drain electrode layer,
wherein the oxide semiconductor layer overlaps in a second region with other one of the source electrode layer and the drain electrode layer and does not overlap with each of the first gate electrode layer and the second gate electrode layer,
wherein the second region has lower crystallinity than the first region, and
wherein in a channel length direction the width of the oxide semiconductor layer is larger than the width of the second gate electrode layer.
6. The semiconductor device according to claim 5 ,
wherein the semiconductor device is configured to apply to the first gate electrode layer a voltage that can be different from a voltage applied to the second gate electrode layer.
7. The semiconductor device according to claim 5 , further comprising a third insulating layer over the second gate electrode layer and a fourth insulating layer over the third insulating layer.
8. The semiconductor device according to claim 5 , wherein the first region comprises a crystal region containing a c-axis aligned crystal.
9. The semiconductor device according to claim 8 , wherein the crystal region includes a part of the top surface of the oxide semiconductor layer.