Methods and apparatuses for two-qubit gate reduction in quantum circuits
The disclosure describes a method, an apparatus, a computer-readable medium, and/or means for reducing two-qubit gates in quantum circuits may include receiving a netlist including information relating to a first plurality of two-qubit quantum gates that form the quantum circuits, performing a controlled gate cancellation operation on the information relating to a first plurality of two-qubit quantum gates to produce a second plurality of two-qubit quantum gates that is functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of two-qubit quantum gates in the first plurality of two-qubit quantum gates is larger than a second number of two-qubit quantum gates in the second plurality of two-qubit quantum gates, generating a new netlist containing information about the second plurality of two-qubit quantum gates, and providing the new netlist to implement a functionality of the quantum circuits based on the second plurality of two-qubit quantum gates.
1. A method for reducing two-qubit gates in quantum circuits, comprising:
receiving information about a quantum circuit for performing a simulation of a physical application, the information including a representation of the quantum circuit by a first sequence of addends;
reordering the addends in the first sequence of addends to produce a second sequence of addends for representation of the quantum circuit, the second sequence of addends conveying information relating to a first plurality of two-qubit quantum gates that form the quantum circuit;
performing a controlled gate cancellation operation on the information relating to a first plurality of two-qubit quantum gates to produce a second plurality of two-qubit quantum gates that is functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of two-qubit quantum gates in the first plurality of two-qubit quantum gates is larger than a second number of two-qubit quantum gates in the second plurality of two-qubit quantum gates;
generating a netlist containing information about the second plurality of two-qubit quantum gates; and
providing the netlist to a quantum information processing (QIP) system to implement a functionality of the quantum circuit to perform the simulation of the physical application.
2. The method of claim 1 , wherein the information about the quantum circuit includes information relating to one or more of controlled gates, R Z gates, H gates, P gates, or P † gates.
3. The method of claim 1 , wherein performing the controlled gate cancellation operation further includes performing one or more H gate cancellation operations.
4. The method of claim 1 , wherein performing the controlled gate cancellation operation further includes performing one or more HPH commutation operations.
5. The method of claim 4 , wherein performing the controlled gate cancellation operation further includes performing one or more CNOT gates cancellation operations.
6. The method of claim 1 , wherein performing the controlled gate cancellation operation further includes performing one or more HP†H transformations.
7. The method of claim 6 , wherein performing the controlled gate cancellation operation further includes performing one or more P gate commutation operations.
8. The method of claim 1 , wherein performing the controlled gate cancellation operation further includes performing one or more HPH transformations.
9. The method of claim 8 , wherein performing the controlled gate cancellation operation further includes performing one or more P † gate commutation operations.
10. The method of claim 1 , wherein performing the controlled gate cancellation operation further includes performing one or more CNOT gate substitutions.
11. The method of claim 1 , wherein the controlled gate cancellation operation maximizes a number of small angle Molmer-Sorensen (MS) gates in the second plurality of two-qubit quantum gates.
12. The method of claim 1 , wherein the physical application is a chemical application or a molecular application.
13. The method of claim 1 , wherein the simulation is a dynamic simulation.
14. The method of claim 1 , wherein for each addend there is a corresponding product of Pauli matrices produced by a transformation.
15. The method of claim 14 , wherein the transformation is a Jordan-Wigner transformation.
16. The method of claim 14 , wherein the transformation is approximated by a Trotterization process.
17. A non-transitory computer readable medium having instructions that, when executed by one or more processors, cause the one or more processors to:
receive information about a quantum circuit for performing a simulation of a physical application, the information including a representation of the quantum circuit by a first sequence of addends:
reorder the addends in the first sequence of addends to produce a second sequence of addends for representation of the quantum circuit, the second sequence of addends conveying information relating to a first plurality of two-qubit quantum gates that form the quantum circuit;
perform a controlled gate cancellation operation on the information relating to a first plurality of two-qubit quantum gates to produce a second plurality of two-qubit quantum gates that is functionally equivalent to the first plurality of two-qubit quantum gates, wherein a first number of two-qubit quantum gates in the first plurality of two-qubit quantum gates is larger than a second number of two-qubit quantum gates in the second plurality of two-qubit quantum gates;
generate a netlist containing information about the second plurality of two-qubit quantum gates; and
provide the netlist to a quantum information processing (QIP) system to implement a functionality of the quantum circuit to perform the simulation of the physical application.
18. The non-transitory computer readable medium of claim 17 , wherein the information about the quantum circuit includes information relating to one or more of controlled R z gates, H gates, P gates, or P † gates.
19. The non-transitory computer readable medium of claim 17 , wherein performing the controlled gate cancellation operation further includes performing one or more H gate cancellation operations.
20. The non-transitory computer readable medium of claim 17 , wherein performing the controlled gate cancellation operation further includes performing one or more HPH commutation operations.
21. The non-transitory computer readable medium of claim 20 , wherein performing the controlled gate cancellation operation further includes performing one or more CNOT gates cancellation operations.
22. The non-transitory computer readable medium of claim 17 , wherein performing the controlled gate cancellation operation further includes performing one or more HP†H transformations.
23. The non-transitory computer readable medium of claim 22 , wherein performing the controlled gate cancellation operation further includes performing one or more P gate commutation operations.
24. The non-transitory computer readable medium of claim 17 , wherein performing the controlled gate cancellation operation further includes performing one or more HPH transformations.
25. The non-transitory computer readable medium of claim 24 , wherein performing the controlled gate cancellation operation further includes performing one or more inverse P gate commutation operations.
26. The non-transitory computer readable medium of claim 17 , wherein performing the controlled gate cancellation operation further includes performing one or more CNOT gate substitutions.