IP Library › Granted Patent US 12,367,411
Granted Patent B2
US 12,367,411 · App. 17/550,436 · Granted Jul 22, 2025

Enablement of sampling-optimization for gate-level simulation

Inventors: Hiroshi Horii (Tokyo, JP); Ikko Hamamura (Tokyo, JP)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06N10/20G06F30/3308G06N10/40G06N10/70G06N10/80
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Quick Facts
Patent No.
US 12,367,411
App. No.
17/550,436
Filed
Dec 14, 2021
Granted
Jul 22, 2025
Kind
B2
Art Unit
2851
USPC
716/100
Abstract

Systems, computer-implemented methods, and computer program products to facilitate sampling-optimization for gate-level simulations are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a cache component that caches a state of a set of qubits within a quantum gate-level simulation after the set of qubits are reset. According to another embodiment the computer executable components further comprise an avoidance component that prevents duplicated simulation of quantum gates in the quantum gate-level simulation by using the cached state of the set of qubits to represent a quantum state produced by a previously simulated quantum gate.

Claims (40)

1. A system comprising:

a memory that stores executable components; and

a processor that executes computer executable components stored in memory, wherein the computer executable components comprise:

a cache component that caches a state of a set of qubits within a quantum gate-level simulation after the set of qubits are reset.

2. The system of claim 1 , further comprising:

a detection component that detects whether the set of qubits in the quantum gate-level simulation are reset.

3. The system of claim 1 , further comprising:

an avoidance component that prevents duplicated simulation of quantum gates in the quantum gate-level simulation by using the cached state of the set of qubits to represent a quantum state produced by a previously simulated quantum gate.

4. The system of claim 1 , further comprising:

a sampling component that takes a sample of all the qubits in the set of qubits when a request for a measurement of a state of a qubit in the set of qubits is received.

5. The system of claim 1 , further comprising:

an evaluation component that evaluates the reset of the set of qubits by buffering the reset without performing it and performing a list of buffered resets when a gate that is not a reset gate is received.

6. The system of claim 1 , wherein the reset of the set of qubits is at a first time and wherein the cache component associates the state of the set of qubits with a list of quantum gates at a second time, wherein the second time is after the first time.

7. The system of claim 1 , further comprising:

a buffering component that buffers gates that are not measured and not reset after setting the state of the set of qubits and updates the buffered gates after a first request for a measurement for a value of a qubit in the set of qubits is received.

8. A computer-implemented method, comprising:

caching, by a system operatively coupled to a processor, a state of a set of qubits within a quantum gate-level simulation after the set of qubits are reset.

9. The computer-implemented method of claim 8 , further comprising:

detecting, by the system, whether the set of qubits in the quantum gate-level simulation are reset.

10. The computer-implemented method of claim 8 , further comprising:

avoiding, by the system, duplicated simulation of quantum gates in the quantum gate-level simulation by using the cached state of the set of qubits to represent a quantum state produced by a previously simulated quantum gate.

11. The computer-implemented method of claim 8 , further comprising:

sampling, by the system, all qubits in the set of qubits when a request for a measurement of a state of a qubit in the set of qubits is received.

12. The computer-implemented method of claim 8 , further comprising:

evaluating, by the system, the reset of the set of qubits by buffering the reset without performing it and performing a list of buffered resets when a gate that is not reset is received.

13. The computer-implemented method of claim 8 , wherein the caching associates the state of the set of qubits with a list of quantum gates at a second time, wherein the second time is after the first time.

14. The computer-implemented method of claim 8 , further comprising:

buffering, by the system, gates that are not measured and not reset after setting the state of the set of qubits and updates the buffered gates after a first request for a measurement for a value of a qubit in the set of qubits is received.

15. A computer program product, the computer program product comprising one or more computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

cache, by the processor, a state of a set of qubits within a quantum gate-level simulation after the set of qubits are reset.

16. The computer program product of claim 15 , the program instructions further executable by the processor to cause the processor to:

detect, by the processor, whether the set of qubits in the quantum gate-level simulation are reset.

17. The computer program product of claim 15 , the program instructions further executable by the processor to cause the processor to:

avoid, by the processor, duplicated simulation of quantum gates in the quantum gate-level simulation by using the cached state of the set of qubits to represent a quantum state produced by a previously simulated quantum gate.

18. The computer program product of claim 15 , the program instructions further executable by the processor to cause the processor to:

sample, by the processor, of all the qubits in the set of qubits when a request for a measurement of a state of a qubit in the set of qubits is received.

19. The computer program product of claim 15 , the program instructions further executable by the processor to cause the processor to:

evaluate, by the processor, the reset of the set of qubits by buffering the reset without performing it and performing a list of buffered resets when a gate that is not a reset gate is received.

20. The computer program product of claim 15 , the program instructions further executable by the processor to cause the processor to:

buffer, by the processor, gates that are not measured and not reset after setting the state of the set of qubits and updates the buffered gates after a first request for a measurement for a value of a qubit in the set of qubits is received.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2021
From: HORII, HIROSHI; HAMAMURA, IKKO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 058386/0316 →
Continuity (1)
Related Publication 20230186129A1 · Jun 15, 2023
References Cited (34)
US 9064067B2 · Wecker · 2015 [cited by applicant]
US 10909286B2 · Johnston · 2021 [cited by applicant]
US 10929294B2 · Brahm · 2021 [cited by examiner]
US 11010517B2 · Nam et al. · 2021 [cited by applicant]
US 11042685B2 · Martiel et al. · 2021 [cited by applicant]
US 11093669B2 · Chen et al. · 2021 [cited by applicant]
US 11100417B2 · Padnault et al. · 2021 [cited by applicant]
US 11341303B2 · Roetteler · 2022 [cited by examiner]
US 11488049B2 · Cao · 2022 [cited by examiner]
US 11507872B2 · Cao · 2022 [cited by examiner]
US 11544614B2 · Horii · 2023 [cited by examiner]
US 20190156239A1 · Martinis et al. · 2019 [cited by applicant]
US 20190378025A1 · Corcoles-Gonzalez et al. · 2019 [cited by applicant]
US 20200134503A1 · Lupton · 2020 [cited by examiner]
US 20200184025A1 · Horii et al. · 2020 [cited by applicant]
US 20200327441A1 · Cao et al. · 2020 [cited by applicant]
US 20200380397A1 · Quintin · 2020 [cited by applicant]
US 20200394547A1 · Cao et al. · 2020 [cited by applicant]
US 20210049496A1 · Kalendarov et al. · 2021 [cited by applicant]
US 20210133617A1 · Sim · 2021 [cited by applicant]
US 20210182724A1 · Zou et al. · 2021 [cited by applicant]
US 20210192114A1 · Boixo Castrillo et al. · 2021 [cited by applicant]
US 20210357797A1 · Karalekas · 2021 [cited by examiner]
CN 110073372A · 2019 [cited by applicant]
A.J. Smith, “Cache Memories,” Computing Surveys, vol. 14, No. 3, Sep. 1982, pp. 473-530. (Year: 1982). [cited by examiner]
J. Doi et al., “Cache Blocking Technique to Large Scale Quantum Computing Simulation on Supercomputers,” 2020 IEEE Int'l; Conference on Quantum Computing and Engineering (QCE), pp. 212-222. (Year: 2020). [cited by examiner]
A. Fatima et al., “Faster Schrodinger-style simulation of quantum circuits,” 2021 IEEE Int'l Symposium on High-Performance Computer Architecture (HPCA), pp. 194-207. (Year: 2021). [cited by examiner]
Gong, M. et al. | “Verification of a resetting protocol for an uncontrolled superconducting qubit”. npj Quantum Information (2020) 6:99; https://doi.org/10.1038/s41534-020-00329-3, 9 pages. [cited by applicant]
Medvidovic, M. et al. | “Classical variational simulation of the Quantum Approximate Optimization Algorithm”. npj Quantum Information (2021) 7:101; https://doi.org/10.1038/s41534-021-00440-z, 7 pages. [cited by applicant]
Li, B. et al. | “Pulse-level noisy quantum circuits with QuTiP”. arXiv:2105.09902v1 [quant-ph] May 20, 2021, 26 pages. [cited by applicant]
Wu, X. et al | “High-fidelity software-defined quantum logic on a superconducting qudit”. arXiv:2005.13165v3 [quant-ph] Oct. 19, 2020, 7 pages. [cited by applicant]
Viamontes, G.F. et al. | “Improving Gate-Level Simulation of Quantum Circuits”. arXiv:quant-ph/0309060v2 Nov. 29, 2003, 22 pages. [cited by applicant]
Openqasm Live Specification | “Classical instructions”. Webpage, https://qiskit.github.io/openqasm/language/classical.html, last accessed Nov. 2, 2021, 5 pages. [cited by applicant]
International Search Report and Written Opinion received for International PCT Application Serial No. PCT/CN2022/108416 dated Oct. 10, 2022, 9 pages. [cited by applicant]