Semiconductor device with electrostatic discharge protection

1. A semiconductor device comprising:

a well region comprising a source region and a drain region, each spaced apart from the other;

a guard ring region disposed around a perimeter of the well region;

an insulating layer disposed, around the perimeter of the well region, on the guard ring region; and

a poly gate disposed, around the perimeter of the well region, on the insulating layer.

2. The semiconductor device of claim 1 further comprising,

a bulk region disposed on an upper surface of the guard ring region adjacent the poly gate.

3. The semiconductor device of claim 2 ,

wherein a drain voltage is applied to the bulk region and the drain region.

4. The semiconductor device of claim 1 ,

wherein a gate voltage is applied to the poly gate.

5. The semiconductor device of claim 1 ,

wherein the well region further comprises a well tap region, and a source voltage is applied to the well tap region and the source region.

6. The semiconductor device of claim 1 further comprising:

a buried impurity layer disposed spaced apart at a depth deeper than a depth of the well region; and

a sink region formed under the guard ring region and disposed to be in contact with the buried impurity layer.

7. The semiconductor device of claim 1 ,

wherein the semiconductor device is a gate-coupled first conductivity type semiconductor device or a gate-coupled second conductivity type semiconductor device.

8. The semiconductor device of claim 1 , wherein the well region is a P-type well region further comprising a well tap region and a gate electrode.

9. The semiconductor device of claim 8 , wherein an epitaxial layer is disposed around the P-type well region.

10. The semiconductor device of claim 9 , wherein an isolation region is disposed between the guard ring region and the P-type well region.

11. A semiconductor device comprising:

a P-type substrate;

a P-type well region, disposed on the P-type substrate, comprising source regions and drain regions each spaced apart from the other;

an N-type well region disposed and spaced apart from the P-type well region on the P-type substrate, the N-type well region comprising the source regions, and the P-type well region comprising the drain regions;

an N-type guard ring region disposed around perimeters of the P-type well region and the N-type well region;

an insulating layer disposed to around the P-type well region and the N-type well region on the N-type guard ring region;

a poly gate disposed, around the perimeters of the P-type well region and the N-type well region, respectively, on the insulating layer; and

a bulk region disposed on the N-type guard ring region adjacent the poly gate.

12. The semiconductor device of claim 11 , wherein the N-type guard ring region comprises:

a first guard ring region forming a closed-loop around the perimeter of the P-type well region; and

a second guard ring region, independent and separate from the first guard ring region, forming a closed-loop around the perimeter of the N-type well region.

13. The semiconductor device of claim 11 , wherein the N-type guard ring region comprises:

a first guard region disposed between the P-type well region and the N-type well region;

a second guard region, connected to the first guard region in a closed loop, surrounding a portion of the perimeter of the P-type well region; and

a third guard region, connected to the first guard region in a closed loop, surrounding a portion of the perimeter of the N-type well region.

14. The semiconductor device of claim 11 , wherein the N-type guard ring region is disposed in a closed loop surrounding both the P-type well region and the N-type well region.

15. The semiconductor device of claim 14 ,

wherein a drain voltage is applied to the bulk region and the drain regions.

16. The semiconductor device of claim 11 ,

wherein a gate voltage is applied to the poly gate.

17. The semiconductor device of claim 11 further comprising:

a first buried layer disposed spaced apart at a depth deeper than a depth of the P-type well; and

a first sink layer formed under the N-type guard ring and disposed to be in contact with the first buried layer.

18. The semiconductor device of claim 17 further comprising:

a second buried layer disposed spaced apart at a depth deeper than a depth of the N-type well; and

a second sink layer formed under the N-type guard ring and disposed to be in contact with the second buried layer.

19. A semiconductor device with electrostatic discharge protection comprising:

a deep well region;

a well region, disposed in the deep well region, comprising source regions and drain regions each spaced apart from the other, respectively;

an insulating layer disposed around a perimeter of the well region on the deep well region;

a poly gate disposed around the perimeter of the well region on the insulating layer; and

a bulk region disposed on the deep well region adjacent the poly gate.

20. The semiconductor device of claim 19 ,

wherein a gate voltage is applied to the poly gate, and a drain voltage is applied to the bulk region.

21. A semiconductor device, comprising:

a P-type well region comprising a well tap region, a source region, a gate electrode, and a drain region;

an N-type deep well region disposed around the P-type well region;

an insulating layer disposed, around the perimeter of the P-type well region, on the N-type deep well region; and

a poly gate disposed, around the perimeter of the P-type well region, on the insulating layer.

22. The semiconductor device of claim 21 , wherein an isolation region disposed between the guard ring region and the poly gate.