Decode circuitry coupled to a memory array

1. An apparatus, comprising:

a memory array physically separate from a semiconductor material;

a trigger device physically separate from the semiconductor material and the memory array, and coupled to an access line of the memory array; and

a select transistor physically separate from the memory array, and coupled to the trigger device and to the access line,

wherein a source/drain region of the select transistor is formed at least partially in the semiconductor material.

2. The apparatus of claim 1 , wherein the access line is a first access line,

wherein the source/drain region of the select transistor is coupled to the first access line, and

wherein the memory array comprises a memory cell between and coupled to the first access line and a second access line.

3. The apparatus of claim 2 , wherein the memory cell is a first memory cell, and

wherein the apparatus further comprises a second memory cell between and coupled to the first access line and a third access line, wherein the third access line is between the first and second memory cells.

4. The apparatus of claim 3 , wherein the select transistor is a first select transistor configured to selectively couple the first access line to a first select voltage node, and

wherein the apparatus further comprises a second select transistor formed at least partially in the semiconductor material and configured to selectively couple the second access line to a first second select voltage node.

5. The apparatus of claim 4 , wherein the first and second select voltage nodes are between the semiconductor material and the memory array.

6. The apparatus of claim 1 , further comprising:

an additional memory array formed over the memory array;

an additional trigger device formed over the memory array and coupled to the additional memory array; and

an additional select device formed over the memory array and coupled to the additional trigger device and the additional memory array.

7. The apparatus of claim 1 , wherein the trigger device is coupled to a pre-decoder.

8. The apparatus of claim 1 , wherein trigger device is formed over the memory array.

9. An apparatus, comprising:

a first access line;

a storage element material formed in contact with the first access line;

a switch material formed on the storage element material;

a second access line formed in contact with the switch material;

a conductive material formed at least partially passing though the storage element material, the switch material, and the second access line;

a trigger device formed in contact with the conductive material, wherein activation of the trigger device causes the switch material to transition from a non-conductive state to a conductive state; and

a select transistor coupled to the second access line, wherein a source/drain region of the select transistor is formed at least partially in a semiconductor material, and

wherein the first access line, the switch material, and the storage element material are physically separate from the semiconductor material.

10. The apparatus of claim 9 , wherein the switch material comprises a voltage-switching material.

11. The apparatus of claim 10 , wherein the voltage-switching material comprises a chalcogenide material.

12. A memory device, comprising:

a first region comprising a memory cell selectively coupled to an access line comprising a storage element material and a switch device configured to selectively couple the storage element material to the access line;

a second region comprising a select transistor formed at least partially in a semiconductor material and coupled to the access line; and

a third region, formed on the first region, comprising:

a trigger device; and

a select device coupled to the trigger device and configured to selectively couple the access line to a global decode node,

wherein the first region and the third region are physically separate from the second region.

13. The memory device of claim 12 , wherein the select device comprises an ovonic threshold switch.

14. The memory device of claim 12 , wherein the trigger device comprises a diode or a transistor.