Boundary design to reduce memory array edge CMP dishing effect
View Patent ↗In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed within a substrate and a plurality of memory devices disposed within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a protrusion extending outward from an upper surface of the first isolation structure. A logic wall is arranged on the protrusion and surrounds the plurality of memory devices.
1. An integrated chip, comprising:
a plurality of transistor devices disposed within a substrate;
a plurality of memory devices disposed within the substrate;
a first isolation structure disposed within the substrate between the plurality of transistor devices and the plurality of memory devices, wherein the first isolation structure has a protrusion extending outward from an upper surface of the first isolation structure; and
a logic wall arranged on the protrusion and surrounding the plurality of memory devices.
2. The integrated chip of claim 1 , wherein the protrusion is laterally offset from opposing outermost sidewalls of the first isolation structure by non-zero distances.
3. The integrated chip of claim 1 , wherein the protrusion laterally extends past opposing sides of the logic wall.
4. The integrated chip of claim 1 , wherein the logic wall comprises:
a gate material disposed over the first isolation structure; and
one or more sidewall spacers laterally surrounding the gate material.
5. The integrated chip of claim 1 , wherein the logic wall has an uppermost surface that is vertically above uppermost surfaces of the plurality of memory devices.
6. The integrated chip of claim 1 , further comprising:
a memory wall disposed vertically over the first isolation structure and laterally separated from the logic wall by a non-zero distance, wherein the memory wall has a bottommost surface that is vertically below a bottommost surface of the logic wall.
7. The integrated chip of claim 6 , wherein the memory wall and the plurality of memory devices comprise a same material.
8. The integrated chip of claim 6 , wherein the memory wall surrounds the plurality of memory devices as viewed from a top-view of the logic wall.
9. The integrated chip of claim 1 , wherein the logic wall has a greater width than respective ones of the plurality of transistor devices.
10. The integrated chip of claim 1 , wherein the protrusion has a width and a height, a ratio of the width to the height is in a range of between approximately 20 and approximately 250.
11. The integrated chip of claim 1 , wherein the protrusion has a height that is in a range of between approximately 150 angstroms and approximately 500 angstroms.
12. An integrated chip, comprising:
a plurality of transistor devices disposed within a substrate;
a plurality of memory devices disposed within the substrate;
a first isolation structure disposed within the substrate between the plurality of transistor devices and the plurality of memory devices;
a memory wall arranged on the first isolation structure and surrounding the plurality of memory devices; and
a logic wall arranged on the first isolation structure and surrounding the memory wall, wherein the logic wall has an uppermost surface that is above uppermost surfaces of both the plurality of memory devices and the memory wall.
13. The integrated chip of claim 12 , wherein the logic wall laterally surrounds the plurality of memory devices.
14. The integrated chip of claim 12 ,
wherein the plurality of memory devices are disposed over a first upper surface of the substrate; and
wherein the first isolation structure protrudes outward from the first upper surface of the substrate.
15. The integrated chip of claim 12 ,
wherein the plurality of memory devices are disposed over a first upper surface of the substrate and the plurality of transistor devices are disposed over a second upper surface of the substrate; and
wherein an imaginary horizontal plane that extends in parallel to and along the second upper surface of the substrate is separated from the first upper surface of the substrate by a non-zero distance.
16. An integrated chip, comprising:
a plurality of transistor devices disposed within a substrate;
a plurality of memory devices disposed within the substrate;
a memory wall arranged between the plurality of transistor devices and the plurality of memory devices, wherein the memory wall continuously extends around the plurality of memory devices; and
a logic wall continuously extending around the memory wall, wherein the logic wall has an uppermost surface arranged along an imaginary horizontal plane that is separated from the memory wall by a non-zero distance.
17. The integrated chip of claim 16 , further comprising:
a first isolation structure disposed between sidewalls of the substrate, the first isolation structure continuously extending from directly below the memory wall to directly below the logic wall.
18. The integrated chip of claim 17 , wherein the first isolation structure has a first outermost sidewall and a second outermost sidewall, a top of the first outermost sidewall is above a top of the second outermost sidewall.
19. The integrated chip of claim 17 , wherein the imaginary horizontal plane is also separated from tops of the plurality of memory devices and the plurality of transistor devices by non-zero distances.
20. The integrated chip of claim 16 , wherein the logic wall and the memory wall comprise different materials.