Package structure and method of fabricating the same

1. A method, comprising:

forming a first pillar portion of a conductive pillar over a carrier;

placing a semiconductor die over the carrier;

encapsulating the first pillar portion and the semiconductor die with an insulating encapsulation;

forming a first opening in the insulating encapsulation to expose a portion of the first pillar portion; and

forming a second pillar portion of the conductive pillar in the first opening defined in the insulating encapsulation, wherein a ratio of a height of the conductive pillar to a bottom width of the conductive pillar ranges from about 5 to about 5n, n is a positive integer greater than 1, and forming the second pillar portion comprises:

forming a first seed layer over the insulating encapsulation and a surface of the first pillar portion exposed by the first opening defined in the insulating encapsulation;

forming a conductive material over the first seed layer; and

polishing the conductive material and the first seed layer until the insulating encapsulation is exposed to form the second pillar portion in the first opening defined in the insulating encapsulation.

2. The method as claimed in claim 1 , wherein a first aspect ratio of the first pillar portion is less than a second aspect ratio of the second pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion, and a first height of the first pillar portion is substantially equal to a second height of the second pillar portion.

3. The method as claimed in claim 2 , wherein forming the first pillar portion comprises:

forming a second seed layer over the carrier;

forming a first patterned photoresist layer over the second seed layer, the first patterned photoresist layer comprising a second opening, and the second seed layer being partially exposed by the second opening;

plating the first pillar portion on an exposed portion of the second seed layer exposed by the second opening;

removing the first patterned photoresist layer; and

removing the second seed layer uncovered by the first pillar portion.

4. The method as claimed in claim 3 , wherein the second seed layer uncovered by the first pillar portion is removed prior art to encapsulating the first pillar portion and the semiconductor die with the insulating encapsulation.

5. The method as claimed in claim 1 , wherein a first aspect ratio of the first pillar portion ranges from about 2.5 to about 2.5n, and n is a positive integer greater than 1.

6. The method as claimed in claim 1 , wherein a second aspect ratio of the second pillar portion ranges from about 7 to about 7n, and n is a positive integer greater than 1.

7. The method as claimed in claim 1 , wherein a level height of a contact interface between the first pillar portion and the second pillar portion is between a level height of an active surface of the semiconductor die and a level height of a back surface of the semiconductor die.

8. The method as claimed in claim 1 , wherein a first width of the first pillar portion is greater than a second width of the second pillar portion.

9. The method as claimed in claim 1 further comprising:

removing the carrier from the semiconductor die and the first pillar portion encapsulated by the insulating encapsulation.

10. The method as claimed in claim 1 further comprising:

forming a redistribution circuit layer over the semiconductor die and the insulating encapsulation, wherein the semiconductor die is electrically connected to the conductive pillar though the redistribution circuit layer.

11. A method, comprising:

laterally encapsulating a first pillar portion and a semiconductor die with an insulating encapsulation;

forming an opening in the insulating encapsulation, and a top surface of the first pillar portion being revealed by the opening;

forming a conductive material covering the insulating encapsulation and filling the opening; and

partially removing the conductive material until the insulating encapsulation is exposed and a second pillar portion is formed in the opening, wherein a ratio of a total height of the first pillar portion and the second pillar portion to a bottom width of the first pillar portion ranges from about 5 to about 5n, and n is a positive integer greater than 1.

12. The method as claimed in claim 11 , wherein a level height of a contact interface between the first pillar portion and the second pillar portion is between a level height of an active surface of the semiconductor die and a level height of a back surface of the semiconductor die.

13. The method as claimed in claim 11 , wherein a first aspect ratio of the first pillar portion ranges from about 2.5 to about 2.5n, and n is a positive integer greater than 1.

14. The method as claimed in claim 11 , wherein a second aspect ratio of the second pillar portion ranges from about 7 to about 7n, and n is a positive integer greater than 1.

15. The method as claimed in claim 11 further comprising:

forming a redistribution circuit layer over the semiconductor die and the insulating encapsulation, wherein the semiconductor die is electrically connected to the conductive pillar though the redistribution circuit layer.

16. A method, comprising:

laterally encapsulating a first pillar portion and a semiconductor die with an insulating encapsulation;

partially removing the insulating encapsulation to reveal a portion of a top surface of e first pillar portion;

forming conductive material covering the insulating encapsulation and the portion of the top surface of the first pillar portion; and

grinding the conductive material until the insulating encapsulation is exposed to form a second pillar portion disposed on the portion of the top surface of the first pillar portion, wherein a ratio of a total height of the first pillar portion and the second pillar portion to a bottom width of the first pillar portion ranges from about 5 to about 5n, and n is a positive integer greater than 1.

17. The method as claimed in claim 16 , wherein a first width of the first pillar portion is greater than a second width of the second pillar portion.

18. The method as claimed in claim 16 , wherein a first aspect ratio of the first pillar portion ranges from about 2.5 to about 2.5n, and n is a positive integer greater than 1.

19. The method as claimed in claim 16 , wherein a second aspect ratio of the second pillar portion ranges from about 7 to about 7n, and n is a positive integer greater than 1.

20. The method as claimed in claim 16 , wherein a level height of a contact interface between the first pillar portion and the second pillar portion is between a level height of an active surface of the semiconductor die and a level height of a back surface of the semiconductor die.