Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
1. An integrated circuit structure, comprising:
a first metal interconnect structure in a first low-k inter-layer dielectric (ILD) layer above a substrate;
a second metal interconnect structure in the first low-k inter-layer dielectric (ILD) layer;
a trench in the first low-k ILD layer, the trench between the first metal interconnect structure and the second metal interconnect structure;
an air gap in the trench;
a hardmask layer directly on the first metal interconnect structure;
an intermediate dielectric layer directly on the hardmask layer, the intermediate dielectric layer having a dielectric constant less than the dielectric constant of the hardmask layer;
a metal oxide layer directly on the intermediate dielectric layer, the metal oxide layer having a dielectric constant greater than the dielectric constant of the intermediate dielectric layer; and
a second low-k ILD layer directly on the metal oxide layer.
2. The integrated circuit structure of claim 1 , wherein the intermediate dielectric layer is further in the trench, the intermediate dielectric layer between the air gap and the first metal interconnect structure, and the intermediate dielectric layer between the air gap and the second metal interconnect structure.
3. The integrated circuit structure of claim 1 , wherein the second low-k ILD layer is further in the trench.
4. The integrated circuit structure of claim 1 , further comprising:
a conductive via in the second low-k ILD layer and through an opening in the metal oxide layer, the intermediate dielectric layer and the hardmask layer, the conductive via directly on and electrically coupled to the first metal interconnect structure.
5. The integrated circuit structure of claim 1 , wherein the metal oxide layer comprises aluminum and oxygen.
6. The integrated circuit structure of claim 1 , wherein the intermediate dielectric layer comprises silicon, oxygen and carbon.
7. The integrated circuit structure of claim 1 , wherein the hardmask layer comprises silicon and nitrogen.
8. The integrated circuit structure of claim 1 , wherein the second low-k ILD layer comprises silicon, oxygen and carbon.
9. The integrated circuit structure of claim 1 , wherein the second low-k ILD layer has a dielectric constant in the range of 2.5-3.1.
10. The integrated circuit structure of claim 1 , wherein the first low-k ILD layer has a dielectric constant in the range of 2.5-3.2.
11. The integrated circuit structure of claim 10 , wherein the first low-k ILD layer comprises silicon, oxygen, carbon and hydrogen.
12. The integrated circuit structure of claim 1 , wherein the first low-k ILD layer comprises silicon, oxygen, carbon and hydrogen.
13. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a metal interconnect structure in a first low-k inter-layer dielectric (ILD) layer above a first metal interconnect structure in a first low-k inter-layer dielectric (ILD) layer above a substrate;
a second metal interconnect structure in the first low-k inter-layer dielectric (ILD) layer;
a trench in the first low-k ILD layer, the trench between the first metal interconnect structure and the second metal interconnect structure;
an air gap in the trench;
a hardmask layer directly on the first metal interconnect structure;
an intermediate dielectric layer directly on the hardmask layer, the intermediate dielectric layer having a dielectric constant less than the dielectric constant of the hardmask layer;
a metal oxide layer directly on the intermediate dielectric layer, the metal oxide layer having a dielectric constant greater than the dielectric constant of the intermediate dielectric layer; and
a second low-k ILD layer directly on the metal oxide layer.
14. The computing device of claim 13 , further comprising:
a memory coupled to the board.
15. The computing device of claim 13 , further comprising:
a communication chip coupled to the board.
16. The computing device of claim 13 , further comprising:
a camera coupled to the board.
17. The computing device of claim 13 , further comprising:
a battery coupled to the board.
18. The computing device of claim 13 , further comprising:
an antenna coupled to the board.
19. The computing device of claim 13 , further comprising:
a global positioning system coupled to the board.
20. The computing device of claim 13 , wherein the component is a packaged integrated circuit die.