Operating different processor cache levels
A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.
1. A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution and a directory structure having data stored in the directory structure with a bookkeeping logic, the cache hierarchy comprising at least a lower hierarchy level entity and a higher hierarchy level entity, the method comprising:
sending a fetch request to the cache hierarchy;
detecting a miss event from the lower hierarchy level entity;
sending a fetch request to the higher hierarchy level entity;
scheduling at least one write pass; and
writing, in the case of a write pass, data into the directory structure to the respective level hierarchy entity instead of writing the data to a fetch address register, (FAR).
2. The computer implemented method of claim 1 , wherein the scheduling of the at least one write pass comprises writing information into a directory administrating the lower hierarchy level entity.
3. The computer implemented method of claim 1 , wherein the scheduling of the at least one write pass is performed without waiting for the reply to the fetch request to the higher hierarchy level entity.
4. The computer implemented method of claim 1 , wherein a third hierarchy level entity is comprised, and the sending the fetch request comprises sending the fetch request to the third hierarchy level entity.
5. The computer implemented method of claim 1 , further comprising scheduling a first write pass and writing directory structures of a lower hierarchy level entity to be invalid.
6. The computer implemented method of claim 1 , further comprising receiving a response from the higher level hierarchy entity.
7. The computer implemented method of claim 1 , further comprising scheduling a second write pass for key and valid information of directories in the lower level hierarchy entity and the higher level hierarchy entity.
8. The computer implemented method of claim 1 , wherein the lower level hierarchy entity is a first level cache of the processor and the higher level hierarchy is a second level cache of the processor.
9. The computer implemented method of claim 8 , wherein a third hierarchy entity is provided that is a further cache or a main memory.
10. The computer implemented method of claim 1 , further comprising determining, based upon a response from the higher level hierarchy entity, as to whether a hit has been encountered.
11. The computer implemented method of claim 10 , further comprising, when a miss has been encountered in the higher level hierarchy entity, and response is received from the next higher level hierarchy entity, writing only key and valid information.
12. A processor having at least a one cache, comprising:
a directory structure for keeping entries written into a memory bank of the cache; and
a fetch address register;
wherein parts of the directory structure are arranged to, at least partially, fulfil a task of the fetch address register; and
wherein the directory structure is arranged to have data written to a respective level hierarch entity.
13. The processor of claim 12 , wherein the directory structure further comprises:
bookkeeping logic for keeping book about which entry is stored; and
data stored in the directory structure.
14. The processor of claim 12 configured to execute a process of:
sending a fetch request to the cache hierarchy;
detecting a miss event from the lower hierarchy level entity;
sending a fetch request to the higher hierarchy level entity; and
scheduling at least one write pass.
15. The processor of claim 14 further configured to execute a process of:
scheduling a first write pass and writing directory structures of a lower hierarchy level entity to be invalid.
16. The processor of claim 14 further configured to execute a process of:
receiving a response from the higher level hierarchy entity.
17. The processor of claim 14 further configured to execute a process of:
scheduling a second write pass for key and valid information of directories in the lower level hierarchy entity and the higher level hierarchy entity.
18. The processor of claim 14 further configured to execute a process of:
determining, based upon a response from the higher level hierarchy entity, as to whether a hit has been encountered.
19. The processor of claim 18 further configured to when a miss has been encountered in the higher level hierarchy entity, and response is received from the next higher level hierarchy entity, writing only key and valid information.