Structure for standard logic performance improvement having a back-side through-substrate-via

1. An integrated chip, comprising:

a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate;

a first conductive pad arranged along a back-side of the first substrate;

a first through-substrate-via (TSV) extending between an interconnect wire of the first plurality of interconnect layers and the first conductive pad;

a second plurality of interconnect layers within a second ILD structure disposed along a front-side of a second substrate that faces away from the first substrate, wherein the second ILD structure surrounds one or more transistor gates disposed along the front-side of the second substrate, and wherein the second substrate is bonded to the first substrate by a first dielectric layer disposed along a back-side of the second substrate facing the first substrate; and

a second TSV extending from an interconnect of the second plurality of interconnect layers to through both the second substrate and the first dielectric layer, wherein the second TSV has a greater width than the first TSV.

2. The integrated chip of claim 1 , further comprising:

a dielectric liner disposed along sidewalls of the first TSV, wherein the dielectric liner laterally separates the first TSV from the first substrate and the first ILD structure.

3. The integrated chip of claim 1 , further comprising:

a first passivation layer disposed directly over and along sidewalls of the first conductive pad, wherein the first passivation layer has a first thickness laterally outside of the first conductive pad and a smaller, second thickness directly over the first conductive pad; and

a second passivation layer disposed directly over and along sidewalls of the first passivation layer.

4. The integrated chip of claim 1 , further comprising:

an additional TSV extending between the interconnect wire of the first plurality of interconnect layers and the first conductive pad, wherein the first TSV and the additional TSV contact a lower surface of the first conductive pad.

5. The integrated chip of claim 1 , further comprising:

a passivation layer disposed over the first conductive pad;

an under bump metallurgy (UBM) layer disposed along sidewalls of the passivation layer and directly contacting an upper surface of the first conductive pad at a location that is completely outside of the first TSV; and

a conductive bump disposed onto the UBM layer.

6. The integrated chip of claim 1 , further comprising:

a second conductive pad arranged along the back-side of the first substrate; and

a passivation layer disposed over the first conductive pad and the second conductive pad, wherein the passivation layer has an uppermost surface that continuously extends from directly over the first conductive pad to directly over the second conductive pad.

7. The integrated chip of claim 1 , wherein the first conductive pad directly contacts a second dielectric layer arranged along the back-side of the first substrate and wherein the first TSV extends through the second dielectric layer.

8. The integrated chip of claim 7 , wherein the first TSV has a different shape than the second TSV as viewed along a cross-sectional view.

9. An integrated chip, comprising:

a plurality of interconnect layers arranged within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate;

a conductive pad arranged along a back-side of the substrate;

a first through-substrate-via (TSV) extending between an interconnect wire of the plurality of interconnect layers and the conductive pad; and

wherein the conductive pad has a first segment extending in a first direction and a second segment extending outward from a first sidewall of the first segment in a second direction perpendicular to the first direction, the first TSV disposed directly below the first segment and a conductive bump disposed directly over the second segment, and wherein an entirety of the first TSV is laterally offset from the conductive bump by non-zero distances along the first direction and along the second direction, the first direction and the second direction parallel to the front-side of the substrate.

10. The integrated chip of claim 9 , further comprising:

a passivation layer arranged over the conductive pad;

an under bump metallurgy (UBM) layer disposed along sidewalls of the passivation layer and contacting an upper surface of the conductive pad; and

wherein the conductive bump is disposed onto the UBM layer and between sidewalls of the passivation layer.

11. The integrated chip of claim 9 , further comprising:

an additional TSV extending through the substrate, wherein both the first TSV and the additional TSV contact a lower surface of the conductive pad and an upper surface of the interconnect wire of the plurality of interconnect layers.

12. The integrated chip of claim 11 , wherein the interconnect wire of the plurality of interconnect layers continuously extends past opposing outermost sidewalls of both the first TSV and the additional TSV.

13. The integrated chip of claim 9 , further comprising:

a second substrate bonded to the substrate; and

a second TSV extending through the second substrate, wherein the second TSV is wider than the first TSV.

14. The integrated chip of claim 9 , wherein the first TSV vertically extends past one or more of the plurality of interconnect layers arranged within the ILD structure.

15. A method of forming an integrated chip, comprising:

forming a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure arranged along a front-side of a first substrate;

forming a second plurality of interconnect layers within a second ILD structure arranged along a front-side of a second substrate;

etching the first substrate and the first ILD structure to define a first opening that has a bottom completely defined by an upper surface of an interconnect wire of the first plurality of interconnect layers;

depositing a conductive material within the first opening to form a first through-substrate-via (TSV);

bonding the second substrate to a back-side of the first substrate after depositing the conductive material within the first opening;

etching a back-side of the second substrate and the second ILD structure, after bonding the second substrate to the back-side of the first substrate, to define a second opening exposing an interconnect wire of the second plurality of interconnect layers;

depositing a second conductive material within the second opening to form a second TSV;

depositing aluminum along the back-side of the second substrate and onto the second TSV; and

patterning the aluminum using photolithography and etching processes to define a conductive pad directly contacting the second TSV.

16. The method of claim 15 , further comprising:

reducing a thickness of the first substrate prior to etching the first substrate and the first ILD structure to define the first opening.

17. The method of claim 15 , wherein the first TSV and the second TSV have different shapes as viewed along a cross-sectional view.

18. The method of claim 15 , further comprising:

prior to depositing the second conductive material within the second opening, performing a thermal oxidation process to form a liner along sidewalls of the second substrate defining the second opening.

19. The method of claim 15 , further comprising:

depositing aluminum onto the back-side of the second substrate after etching the back-side of the second substrate to define the second opening.

20. The method of claim 15 , wherein the interconnect wire of the first plurality of interconnect layers is disposed on a metal interconnect wire layer that is a closest metal interconnect wire layer to the first substrate.