Power-efficient programming of magnetic memory

1. A method for programming a memory cell that includes a transistor and a memory element coupled in series between a first conductive line and a second conductive line, the method including the steps of:

applying a voltage across the memory cell, the voltage being sufficiently high to enable switching of the memory element from an initial resistance state to a target resistance state;

determining the initial resistance state of the memory element;

comparing the initial resistance state with the target resistance state;

if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state; and

if the initial resistance state and the target resistance state are different, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state,

wherein the step of determining the initial resistance state of the memory element is carried out by a first sense amplifier and the step of continually monitoring the voltage is carried out by a second sense amplifier.

2. The method of claim 1 , further comprising the step of concluding that the memory element is defective if the initial resistance state and the target resistance state are different and no substantial change in the voltage is detected after a time period.

3. The method of claim 1 , wherein the first sense amplifier is operable to connect to the first conductive line.

4. The method of claim 1 , wherein the second sense amplifier is operable to connect to the first conductive line and the second conductive line.

5. The method of claim 1 , wherein the first sense amplifier is operable to connect to the first conductive line and the second sense amplifier is operable to connect to the first conductive line and the second conductive line.

6. The method of claim 1 , wherein the transistor is disposed adjacent to the first conductive line and the memory element is disposed adjacent to the second conductive line.

7. The method of claim 1 , wherein the transistor is disposed adjacent to the second conductive line and the memory element is disposed adjacent to the first conductive line.

8. The method of claim 1 , wherein the memory element includes a magnetic tunnel junction (MTJ).

9. The method of claim 1 , wherein the step of applying a voltage across the memory cell is performed by activating a pull-up transistor coupled to the first conductive line and a pull-down transistor coupled to the second conductive line.

10. The method of claim 9 , wherein the pull-up transistor and the pull-down transistor remain activated until the memory element is in the target resistance state.

11. The method of claim 1 , wherein the step of determining the initial resistance state of the memory element is carried out by comparing with a reference cell.

12. The method of claim 1 , wherein the first conductive line is a bit line and the second conductive line is a word line.

13. The method of claim 1 , wherein the first conductive line is a word line and the second conductive line is a bit line.