Metal gates of transistors having reduced resistivity
A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.
1. An integrated circuit device comprising:
a semiconductor region;
a gate dielectric over the semiconductor region;
a gate electrode over a bottom portion of the gate dielectric;
a gate contact plug over and contacting the gate electrode;
a source/drain region adjacent to the gate electrode;
a source/drain silicide region over and contacting the source/drain region; and
a source/drain contact plug over and contacting the source/drain silicide region, wherein a conductive region selected from the group consisting of the gate electrode, the source/drain contact plug, and the gate contact plug comprises a metal silicide layer.
2. The integrated circuit device of claim 1 , wherein the conductive region further comprises a non-silicide metal layer over the metal silicide layer, and the non-silicide metal layer comprises a same metal as the metal silicide layer.
3. The integrated circuit device of claim 2 , wherein the non-silicide metal layer and the metal silicide layer comprise cobalt.
4. The integrated circuit device of claim 3 , wherein the non-silicide metal layer is free from elements other than cobalt.
5. The integrated circuit device of claim 1 , wherein the conductive region comprises the source/drain contact plug, and the source/drain contact plug comprises a metal nitride layer, and wherein the metal silicide layer and the source/drain silicide region are separated from each other by the metal nitride layer.
6. The integrated circuit device of claim 5 , wherein the metal silicide layer contacts a top surface of the metal nitride layer, and the source/drain silicide region contacts a bottom surface of the metal nitride layer.
7. The integrated circuit device of claim 1 , wherein the conductive region comprises the gate electrode, and the gate electrode further comprises a non-silicide conductive layer over the metal silicide layer.
8. The integrated circuit device of claim 1 , wherein the conductive region comprises the gate contact plug, and the integrated circuit device further comprises:
gate spacers on opposing sides of the gate electrode, wherein the gate contact plug extends to a level lower than top surfaces of the gate spacers.
9. The integrated circuit device of claim 1 further comprising an additional gate contact plug over and contacting the gate contact plug, wherein a sidewall of the additional gate contact plug has a tilt angle in a range between about 80 degrees and about 90 degrees.
10. An integrated circuit device comprising:
a gate electrode;
a source/drain region adjacent to the gate electrode;
a source/drain silicide region over the source/drain region; and
a source/drain contact plug over and electrically coupling to the source/drain region, wherein the source/drain contact plug comprises:
a metal nitride layer; and
a metal silicide layer over a bottom portion of the metal nitride layer.
11. The integrated circuit device of claim 10 , wherein the source/drain contact plug further comprises a non-silicide metal-containing layer over the metal silicide layer.
12. The integrated circuit device of claim 11 , wherein the non-silicide metal-containing layer is a cobalt layer.
13. The integrated circuit device of claim 11 , wherein the metal silicide layer and the non-silicide metal-containing layer comprise a same metal.
14. The integrated circuit device of claim 13 , wherein an entirety of the non-silicide metal-containing layer is formed of cobalt having a uniform resistivity, and the non-silicide metal-containing layer is substantially free from elements other than cobalt.
15. The integrated circuit device of claim 10 , wherein the source/drain silicide region and the metal silicide layer contact opposing surfaces of the metal nitride layer.
16. The integrated circuit device of claim 10 , wherein the metal nitride layer comprises a metal different from metals of the source/drain silicide region and the metal silicide layer.
17. The integrated circuit device of claim 10 , wherein the metal silicide layer has a gradient percentage of silicon.
18. An integrated circuit device comprising:
a transistor comprising:
a semiconductor region;
a gate stack overlying the semiconductor region;
a source/drain region adjacent to the gate stack; and
a contact plug electrically connecting to one of the gate stack and the source/drain region, wherein the contact plug comprises:
a cobalt silicide layer; and
a non-silicide cobalt-containing layer over the cobalt silicide layer.
19. The integrated circuit device of claim 18 further comprising a metal nitride layer underlying and contacting the cobalt silicide layer.
20. The integrated circuit device of claim 18 , wherein the cobalt silicide layer has a gradient cobalt percentage.