Display apparatus
A display apparatus includes a display panel including a plurality of pixels configured to display an image, each of at least one of the plurality of pixels including a pixel circuit and a light emitting device connected to the pixel circuit, wherein the pixel circuit includes a driving transistor controlling a driving current flowing at the light emitting device, a data supply transistor selectively providing a data voltage to a first node which is a source electrode of the driving transistor, a first light emitting control transistor selectively connecting the first node to a second node which is an electrode of the light emitting device, a first capacitor connected between the second node and a fourth node which is a gate electrode of the driving transistor, and a second capacitor connected between the second node and a gate electrode of the data supply transistor.
1. A display apparatus comprising:
a display panel including a plurality of pixels configured to display an image,
each of at least one of the plurality of pixels including a pixel circuit and a light emitting device connected to the pixel circuit,
wherein the pixel circuit includes:
a driving transistor controlling a driving current flowing at the light emitting device;
a data supply transistor selectively providing a data voltage to a first node which is at a source electrode of the driving transistor;
a first light emitting control transistor selectively connecting the first node to a second node which is at an electrode of the light emitting device;
a first capacitor connected between the second node and a fourth node which is at a gate electrode of the driving transistor; and
a second capacitor connected between the second node and a gate electrode of the data supply transistor.
2. The display apparatus of claim 1 , wherein the second capacitor drops a voltage of the second node in synchronization with a falling time of a second scan signal supplied to the data supply transistor.
3. The display apparatus of claim 1 , wherein the pixel circuit drops a voltage of the second node in synchronization with a falling time of a first scan signal supplied to an initialization transistor connected to the fourth node.
4. The display apparatus of claim 1 , wherein during each of an initialization period and a sampling period, the pixel circuit drops a voltage of the second node in synchronization with a falling time of a first scan signal supplied to an initialization transistor connected to the fourth node.
5. The display apparatus of claim 1 , wherein the pixel circuit further includes:
a first light emitting control transistor selectively connecting the first node and the second node; and
a first initialization transistor selectively providing an initialization voltage to the second node.
6. The display apparatus of claim 5 , wherein the pixel circuit further includes:
a second light emitting control transistor selectively providing a driving voltage to a third node which is at a drain electrode of the driving transistor; and
a second initialization transistor selectively connecting the third node to the fourth node.
7. The display apparatus of claim 6 , wherein
the each of at least one of the plurality of pixels is driven through an initialization period, a programming period, a sampling period, and an emission period, and
the first initialization transistor is turned on during the initialization period and the sampling period based on a first scan signal provided from a first scan line, and provides the initialization voltage to the second node.
8. The display apparatus of claim 7 , wherein
the second initialization transistor is turned on during the initialization period and the sampling period based on the first scan signal, and provides a voltage of the third node to the fourth node.
9. The display apparatus of claim 7 , wherein
the data supply transistor is turned on during the programming period and the sampling period based on a second scan signal provided from a second scan line, and provides the data voltage to the first node.
10. The display apparatus of claim 9 , wherein
the second capacitor stores a difference voltage between the second scan line and the second node.
11. The display apparatus of claim 9 , wherein
the second capacitor drops a voltage of the second node in synchronization with a falling time of the second scan signal.
12. The display apparatus of claim 9 , wherein
the second capacitor drops a voltage of the second node to a threshold voltage or lower of the light emitting device when the data voltage corresponds to a predetermined minimum value.
13. The display apparatus of claim 7 , wherein
the first light emitting control transistor is turned on during the emission period based on a first emission signal provided from a first emission line, and provides a voltage of the first node to the second node.
14. The display apparatus of claim 7 , wherein
the second light emitting control transistor is turned on during the initialization period and the emission period based on a second emission signal provided from a second emission line, and provides the driving voltage to the third node.
15. A pixel circuit for driving an organic light emitting diode in a pixel of a display device, the pixel circuit comprising:
a driving transistor configured to supply a driving current to the organic light emitting diode;
a data supply transistor configured to selectively provide a data voltage to a first node which is at a source electrode of the driving transistor;
a first light emitting control transistor configured to selectively connect the first node to a second node which is at an electrode of the organic light emitting diode; and
a second capacitor connected between the second node and a gate electrode of the data supply transistor,
wherein the second capacitor drops a voltage of the second node in synchronization with a falling time of a second scan signal supplied to the data supply transistor.
16. The pixel circuit of claim 15 , further comprising:
a first capacitor connected between the second node and a fourth node which is at a gate electrode of the driving transistor,
wherein the pixel circuit drops a voltage of the second node in synchronization with a falling time of a first scan signal supplied to a first initialization transistor connected to the fourth node.
17. The pixel circuit of claim 16 , further comprising:
a first light emitting control transistor selectively connecting the first node and the second node; and
the first initialization transistor selectively providing an initialization voltage to the second node.
18. The pixel circuit of claim 17 , further comprising:
a second light emitting control transistor selectively providing a driving voltage to a third node which is at a drain electrode of the driving transistor; and
a second initialization transistor selectively connecting the third node to the fourth node.
19. The pixel circuit of claim 16 , wherein during each of an initialization period and a sampling period, the pixel circuit drops a voltage of the second node in synchronization with a falling time of the first scan signal.
20. The pixel circuit of claim 15 , wherein the second capacitor further drops the voltage of the second node to a threshold voltage or lower of the organic light emitting diode when the data voltage corresponds to a predetermined minimum value.