Pixel and organic light emitting display device comprising the same
A pixel for an organic light emitting display device includes an organic light emitting diode that emits light by a driving current, a driving transistor configured to control the driving current, a first transistor to connect the second node and the third node, a second transistor to apply a data voltage to the first node, a third transistor to apply a high-potential driving voltage to the second node, a fourth transistor that forms a current path between the driving transistor and the organic light emitting diode, a fifth transistor to apply an initial voltage to the driving transistor, a sixth transistor configured to apply a reset voltage to a fourth node which is an anode electrode of the organic light emitting diode, a seventh transistor configured to apply the high-potential driving voltage to the fifth node, and an eighth transistor configured to apply a reference voltage to the fifth node.
1. A pixel for an organic light emitting display device comprising:
an organic light emitting diode that emits light by a driving current;
a driving transistor configured to control the driving current, the driving transistor including a source electrode as a first node, a gate electrode as a second node, and a drain electrode as a third node;
a first transistor configured to connect the second node and the third node;
a second transistor configured to apply a data voltage (Vdata) to the first node;
a third transistor configured to apply a driving voltage (VDD) to the second node;
a fourth transistor that forms a current path between the driving transistor and the organic light emitting diode;
a fifth transistor configured to apply an initial voltage to the driving transistor;
a sixth transistor configured to apply a reset voltage to a fourth node which is an anode electrode of the organic light emitting diode;
a storage capacitor that includes one electrode connected to the second node and another electrode connected to a fifth node;
a seventh transistor configured to apply the driving voltage to the fifth node; and
an eighth transistor configured to apply a reference voltage (Vref) to the fifth node,
wherein the third transistor is turned on during at least a partial period of a period during which the fourth transistor is turned off.
2. The pixel of claim 1 , wherein the first transistor includes a drain electrode connected to the third node, a source electrode connected to the second node, and a gate electrode connected to a first scan signal line for transmitting a first scan signal,
the second transistor includes a source electrode connected to a data line, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line for transmitting a second scan signal,
the third transistor includes a source electrode connected to a driving voltage line for transmitting the driving voltage, a drain electrode connected to the first node, and a gate electrode connected to a third scan signal line for transmitting a third scan signal,
the fourth transistor includes a source electrode connected to the third node, a drain electrode connected to the fourth node, and a gate electrode connected to an emission signal line for transmitting an emission signal,
the fifth transistor includes a source electrode connected to an initial voltage line for transmitting the initial voltage, a drain electrode connected to the second node, and a gate electrode connected to a first scan signal line at a previous stage transmitting a first scan signal at the previous stage,
the sixth transistor includes a source electrode connected to a reset voltage line for transmitting the reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to a fourth scan signal line for transmitting a fourth scan signal,
the seventh transistor includes a source electrode connected to the driving voltage line, a drain electrode connected to the fifth node, and a gate electrode connected to the emission signal line, and
the eighth transistor includes a source electrode connected to a reference voltage line for transmitting the reference voltage, a drain electrode connected to the fifth node, and a gate electrode connected to the fourth scan signal line.
3. The pixel of claim 1 , wherein the first transistor includes a drain electrode connected to the third node, a source electrode connected to the second node, and a gate electrode connected to a first scan signal line for transmitting a first scan signal,
the second transistor includes a source electrode connected to a data line, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line for transmitting a second scan signal,
the third transistor includes a source electrode connected to a driving voltage line for transmitting the driving voltage, a drain electrode connected to the first node, and a gate electrode connected to a fifth scan signal line for transmitting a fifth scan signal,
the fourth transistor includes a source electrode connected to the third node, a drain electrode connected to the fourth node, and a gate electrode connected to an emission signal line for transmitting an emission signal,
the fifth transistor includes a source electrode connected to an initial voltage line for transmitting the initial voltage, a drain electrode connected to the third node, and a gate electrode connected to a third scan signal line for transmitting a third scan signal,
the sixth transistor includes a source electrode connected to a reset voltage line for transmitting the reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to the third scan signal line,
the seventh transistor includes a source electrode connected to the driving voltage line, a drain electrode connected to the fifth node, and a gate electrode connected to the emission signal line, and
the eighth transistor includes a source electrode connected to a reference voltage line for transmitting the reference voltage, a drain electrode connected to the fifth node, and a gate electrode connected to a fourth scan signal line for transmitting a fourth scan signal.
4. The pixel of claim 1 , wherein the first transistor includes a drain electrode connected to the third node, a source electrode connected to the second node, and a gate electrode connected to a first scan signal line for transmitting a first scan signal,
the second transistor includes a source electrode connected to a data line, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line for transmitting a second scan signal,
the third transistor includes a source electrode connected to a driving voltage line for transmitting the driving voltage, a drain electrode connected to the first node, and a gate electrode connected to the first scan signal line,
the fourth transistor includes a source electrode connected to the third node, a drain electrode connected to the fourth node, and a gate electrode connected to an emission signal line for transmitting an emission signal,
the fifth transistor includes a source electrode connected to an initial voltage line for transmitting the initial voltage, a drain electrode connected to the third node, and a gate electrode connected to a third scan signal line for transmitting a third scan signal,
the sixth transistor includes a source electrode connected to a reset voltage line for transmitting the reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to the third scan signal line,
the seventh transistor includes a source electrode connected to the driving voltage line, a drain electrode connected to the fifth node, and a gate electrode connected to the emission signal line, and
the eighth transistor includes a source electrode connected to a reference voltage line for transmitting the reference voltage, a drain electrode connected to the fifth node, and a gate electrode connected to a fourth scan signal line for transmitting a fourth scan signal.