Display apparatus

1. A display apparatus comprising:

a plurality of pixels configured to display an image,

wherein each of at least one of the plurality of pixels includes a pixel circuit and a light emitting device connected to the pixel circuit,

wherein the plurality of pixels is configured to be driven through a plurality of signals according to an initialization period, a programming period, a sampling period, and an emission period,

wherein the plurality of signals includes:

a first scan signal having a high level in the initialization period and the sampling period, and having a low level in the programming period and the emission period; and

a second scan signal having a high level in the programming period and the sampling period, and having a low level in the initialization period and the emission period,

wherein the pixel circuit includes:

a driving transistor turned on based on a voltage of a fourth node which is a gate electrode of the driving transistor and selectively connecting a first node which is at a source electrode of the driving transistor to a third node which is a drain electrode of the driving transistor;

a data supply transistor selectively providing a data voltage to the first node which is at the source electrode of the driving transistor;

a first light emitting control transistor configured to selectively connect the first node to a second node which is an anode electrode of the light emitting device;

a first scan line connected to a gate electrode of a first initialization transistor and a gate electrode of a second initialization transistor which is configured to selectively connect the third node to the fourth node; and

a second scan line connected to a gate electrode of the data supply transistor,

a voltage of the second node being dropped in synchronization with a falling time of the first scan signal of the initialization period, and

wherein the first scan line supplies the first scan signal and the second scan line supplies the second scan signal.

2. The display apparatus of claim 1 ,

wherein the plurality of signals further includes:

a first emission signal having a high level in the emission period, and having a low level in the initialization period, the programming period, and the sampling period;

a second emission signal having a high level during the initialization period and the emission period, and having a low level during the programming period and the sampling period.

3. The display apparatus of claim 1 ,

wherein the pixel circuit further includes:

a first capacitor connected between the second node and the fourth node; and

a second capacitor connected between the second node and the gate electrode of the data supply transistor.

4. The display apparatus of claim 1 ,

wherein the first initialization transistor selectively provides an initialization voltage to the second node.

5. The display apparatus of claim 4 ,

wherein the pixel circuit further includes:

a second light emitting control transistor selectively providing a driving voltage to the third node; and

the second initialization transistor selectively connecting the third node to the fourth node.

6. The display apparatus of claim 5 ,

wherein the first initialization transistor is turned on during the initialization period and the sampling period based on the first scan signal provided from the first scan line, and provides the initialization voltage to the second node.

7. The display apparatus of claim 6 ,

wherein the data supply transistor is turned on during the programming period and the sampling period based on the second scan signal provided from the second scan line, and provides the data voltage to the first node.

8. The display apparatus of claim 7 ,

wherein the second capacitor drops a voltage of the second node to a threshold voltage or lower of the light emitting device when the data voltage corresponds to a predetermined minimum value.

9. A display apparatus comprising:

a plurality of pixels configured to display an image,

wherein each of at least one of the plurality of pixels includes a pixel circuit and a light emitting device connected to the pixel circuit,

wherein a plurality of signals are configured to drive the plurality of pixels according to an initialization period, a programming period, a sampling period, and an emission period,

wherein the plurality of signals includes:

a first scan signal having a high level in the initialization period and the sampling period, and having a low level in the programming period and the emission period; and

a second scan signal having a high level in the programming period and the sampling period, and having a low level in the initialization period and the emission period,

wherein the pixel circuit includes:

a driving transistor turned on based on a voltage of a fourth node which is a gate electrode of the driving transistor and selectively connecting a first node which is at a source electrode of the driving transistor to a third node which is a drain electrode of the driving transistor;

a data supply transistor selectively providing a data voltage to the first node which is at the source electrode of the driving transistor;

a first light emitting control transistor configured to selectively connect the first node to a second node which is an anode electrode of the light emitting device;

a first scan line connected to a gate electrode of a first initialization transistor and a gate electrode of a second initialization transistor which is configured to selectively connect the third node to the fourth node; and

a second scan line connected to a gate electrode of the data supply transistor,

a voltage of the second node being dropped in synchronization with a falling time of the first scan signal of the sampling period, and

wherein the first scan line supplies the first scan signal and the second scan line supplies the second scan signal.

10. The display apparatus of claim 9 ,

wherein the voltage of the second node is further dropped in synchronization with a falling time of the second scan signal after the sampling period.

11. The display apparatus of claim 9 ,

wherein the plurality of signals further includes:

a first emission signal having a high level in the emission period, and having a low level in the initialization period, the programming period, and the sampling period, the first emission signal being supplied to a gate electrode of the first light emitting control transistor; and

a second emission signal having a high level during the initialization period and the emission period, and having a low level during the programming period and the sampling period, the second emission signal being supplied to a gate electrode of a second light emitting control transistor.

12. The display apparatus of claim 9 ,

wherein the pixel circuit further includes:

a first capacitor connected between the second node and the fourth node which is at the gate electrode of the driving transistor; and

a second capacitor connected between the second node and the gate electrode of the data supply transistor.

13. The pixel circuit of claim 12 ,

wherein the second capacitor further drops the voltage of the second node to a threshold voltage or lower of the organic light emitting diode when the data voltage corresponds to a predetermined minimum value.

14. A display apparatus comprising:

a plurality of pixels configured to display an image,

wherein each of at least one of the plurality of pixels includes a pixel circuit and a light emitting device connected to the pixel circuit,

wherein a plurality of signals are configured to drive the plurality of pixels according to an initialization period, a programming period, a sampling period, and an emission period,

wherein the plurality of signals includes:

a first scan signal having a high level in the initialization period and the sampling period, and having a low level in the programming period and the emission period; and

a second scan signal having a high level in the programming period and the sampling period, and having a low level in the initialization period and the emission period,

wherein the pixel circuit includes:

a driving transistor turned on based on a voltage of a fourth node which is a gate electrode of the driving transistor and selectively connecting a first node which is at a source electrode of the driving transistor to a third node which is a drain electrode of the driving transistor;

a data supply transistor selectively providing a data voltage to the first node which is at the source electrode of the driving transistor;

a first light emitting control transistor configured to selectively connect the first node to a second node which is an anode electrode of the light emitting device;

a first scan line connected to a gate electrode of a first initialization transistor and a gate electrode of a second initialization transistor which is configured to selectively connect the third node to the fourth node; and

a second scan line connected to a gate electrode of the data supply transistor,

a voltage of the second node being dropped in synchronization with a falling time of the second scan signal after the sampling period, and

wherein the first scan line supplies the first scan signal and the second scan line supplies the second scan signal.

15. The display apparatus of claim 14 ,

Wherein the plurality of signals further includes:

a first emission signal having a high level in the emission period, and having a low level in the initialization period, the programming period, and the sampling period, the first emission signal being supplied to a gate electrode of the first light emitting control transistor; and

a second emission signal having a high level during the initialization period and the emission period, and having a low level during the programming period and the sampling period, the second emission signal being supplied to a gate electrode of a second light emitting control transistor.