Method for developing a process for compiling a quantum circuit on a quantum processor and such process
A method for developing a method for compiling a quantum circuit on a quantum processor, comprising: a selection step: of a quantum circuit, of a quantum processor whereupon to compile the quantum circuit, of a set of quantum gates that can be executed on the selected quantum processor, of a metric, a meta-heuristic, a step of division of the selected quantum circuit into quantum sub-circuits, a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor to comprise only quantum gates that can be executed by the selected quantum processor, a second step of re-writing of the quantum sub-circuits, by the selected meta-heuristic, to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, improving the selected metric, a step of regrouping of the quantum sub-circuits in a quantum circuit compilable by the selected quantum processor.
1. A method for developing a method for compiling a quantum circuit on a quantum processor, comprising:
a selection step:
of a quantum circuit,
of a quantum processor whereupon to compile the quantum circuit,
of a set of executable quantum gates on the selected quantum processor, based on the selected quantum processor,
of an optimization metric,
of a heuristic or meta-heuristic,
a step of division of the selected quantum circuit into quantum sub-circuits,
a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor so that they comprise only quantum gates that can be executed by the selected quantum processor,
a second step of re-writing of the quantum sub-circuits according to the selected heuristic or meta-heuristic, in order to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, improving the selected metric,
a step of regrouping of the quantum sub-circuits in a quantum circuit compilable by the selected quantum processor.
2. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 1 , wherein the second step of re-writing comprises:
an iteration loop subsequently comprising:
a step of obtaining of quantum sub-circuits resulting from the first step of re-writing,
a step of re-writing of said quantum sub-circuits into quantum sub-circuits comprising quantum gates that can be executed by the processor improving the selected metric,
a step of regrouping of the quantum sub-circuits to obtain a compilable quantum circuit,
a retroaction step, via the selected heuristic or meta-heuristic, resulting in a new step of re-writing of the quantum sub-circuits resulting from the first step of re-writing according to a selected metric score associated with the compilable quantum circuit, to attain:
either an extreme score threshold for the metric selected,
or a maximum threshold of iterations in the loop.
3. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 1 , wherein:
a score equal to less than infinity is associated with the quantum gates that cannot be executed on the selected quantum processor,
a score equal to zero or to another constant value is associated with the quantum gates that can be executed on the selected quantum processor.
4. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 1 , wherein the heuristic or meta-heuristic for optimization re-writes the quantum sub-circuits by:
changing a sequential order of the quantum gates of the quantum sub-circuits,
and/or merging several quantum gates into a single quantum gate,
and/or replacing the two-qubit quantum gates or more than two-qubits quantum gates with one-qubit quantum gates.
5. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 1 , wherein the selected heuristic or meta-heuristic is a simulated annealing.
6. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 2 , wherein:
the maximum threshold of iterations in the loop is predetermined based on at least one selected quantum processor and/or quantum circuit.
7. A method for developing a method for compiling a quantum circuit on a quantum processor, comprising:
a selection step:
of a quantum circuit,
of a quantum processor whereupon to compile the quantum circuit,
of a set of executable quantum gates on the selected quantum processor, based on the selected quantum processor,
a step of division of the selected quantum circuit into quantum sub-circuits,
a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor so that they comprise only quantum gates that can be executed by the selected quantum processor,
a second step of re-writing of the quantum sub-circuits by application of a simulated annealing, so as to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, reducing a number of quantum gates,
a step of regrouping of the quantum sub-circuits in a quantum circuit compilable by the selected quantum processor.
8. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 7 , wherein the second step of re-writing comprises:
an iteration loop subsequently comprising:
a step of obtaining of quantum sub-circuits resulting from the first step of re-writing,
a step of re-writing of said quantum sub-circuits into quantum sub-circuits comprising quantum gates that can be executed by the processor and reducing the number of quantum gates,
a step of regrouping of the quantum sub-circuits to obtain a compilable quantum circuit,
a retroaction step, via the simulated annealing, resulting in a new step of re-writing of the quantum sub-circuits resulting from the first re-writing step based on the number of quantum gates in the compilable quantum circuit, to attain:
either an extreme score threshold for the metric selected,
or a maximum threshold of iterations in the loop.
9. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 8 , wherein:
the maximum threshold of iterations in the loop is predetermined based on at least one selected quantum processor and/or quantum circuit.
10. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 7 , wherein:
a score equal to less than infinity is associated with the quantum gates that cannot be executed on the selected quantum processor,
a score equal to zero or to another constant value is associated with the quantum gates that can be executed on the selected quantum processor.
11. The method for developing a method for compiling a quantum circuit on a quantum processor according to claim 7 , wherein the simulated annealing re-writes the quantum sub-circuits by:
changing the sequential order of the quantum gates of the quantum sub-circuits,
and/or merging several quantum gates into a single quantum gate,
and/or replacing the one-qubit quantum gates or more than two-qubits quantum gates with one-qubit quantum gates.
12. A method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor, comprising:
a step of division of the selected quantum circuit into quantum sub-circuits,
a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor so that they comprise only quantum gates that can be executed by the selected quantum processor,
a second step of re-writing of the quantum sub-circuits according to a selected heuristic or meta-heuristic, in order to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, improving a selected metric,
a step of regrouping of the quantum sub-circuits in a compiled quantum circuit.
13. The method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor according to claim 12 , wherein the second step of re-writing comprises:
an iteration loop subsequently comprising:
a step of obtaining of quantum sub-circuits resulting from the first step of re-writing,
a step of re-writing of said quantum sub-circuits into quantum sub-circuits comprising quantum gates that can be executed by the processor improving the selected metric,
a step of regrouping of the quantum sub-circuits to obtain a compiled quantum circuit,
a retroaction step, via the selected heuristic or meta-heuristic, resulting in a new step of re-writing of the quantum sub-circuits based on a selected metric score, as a function of the compilable quantum circuit, to attain:
either an extreme score threshold for the metric selected,
or a maximum threshold of iterations in the loop.
14. The method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor according to claim 13 , wherein:
a score equal to less than infinity is associated with the quantum gates that cannot be executed on the selected quantum processor,
a score equal to zero or to another constant value is associated with the quantum gates that can be executed on the selected quantum processor.
15. The method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor according to claim 12 , wherein the heuristic or meta-heuristic for optimization re-writes the quantum sub-circuits by:
changing the sequential order of the quantum gates of the quantum sub-circuits,
and/or merging several quantum gates into a single quantum gate, and/or replacing one-qubit quantum gates or more than two-qubits quantum gates with one-qubit quantum gates.
16. The method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor according to claim 12 , wherein the heuristic or meta-heuristic is a simulated annealing.
17. A method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor, comprising:
a step of division of the selected quantum circuit into quantum sub-circuits,
a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor so that they comprise only quantum gates that can be executed by the selected quantum processor,
a second step of re-writing of the quantum sub-circuits by application of a simulated annealing, so as to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, reducing the number of quantum gates,
a step of regrouping of the quantum sub-circuits in a compiled quantum circuit.
18. The method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor according to claim 17 , wherein the second step of re-writing comprises:
an iteration loop subsequently comprising:
a step of obtaining of quantum sub-circuits resulting from the first step of re-writing,
a step of re-writing of said quantum sub-circuits into quantum sub-circuits comprising quantum gates that can be executed by the processor reducing the number of quantum gates,
a step of regrouping of the quantum sub-circuits to obtain a compilable quantum circuit,
a retroaction step, via the simulated annealing, resulting in a new step of re-writing the quantum sub-circuits based on the number of quantum gates in the compilable quantum circuit, to attain:
either an extremal score threshold for the metric selected,
or a maximum threshold of iterations in the loop.
19. The method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor according to claim 18 , wherein:
the maximum iteration in the loop is predetermined.
20. The method for compiling a quantum circuit on a quantum processor by the use of a set of quantum gates that can be executed on the quantum processor according to claim 17 , wherein the simulated annealing re-writes the quantum sub-circuits by:
changing the sequential order of the quantum gates of the quantum sub-circuits,
and/or merging several quantum gates into a single quantum gate,
and/or replacing one-qubit quantum gates or more than two-qubits quantum gates with one-qubit quantum gates.