Vertical field effect transistor with reduced parasitic capacitance
Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.
1. A method for forming a semiconductor device, the method comprising:
forming a semiconductor fin on a substrate;
forming a stepped bottom spacer on a surface of the substrate, the stepped bottom spacer comprising a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, the first portion defining a near-channel region and the second portion defining a non-channel region;
forming a stepped gate over a channel region of the semiconductor fin, the stepped gate comprising a first portion positioned on the near-channel region of the stepped bottom spacer and a second portion positioned on the non-channel region of the stepped bottom spacer; and
forming a stepped top spacer on the stepped gate.
2. The method of claim 1 , wherein the near-channel region of the stepped bottom spacer is positioned between the non-channel region of the stepped bottom spacer and a sidewall of the semiconductor fin.
3. The method of claim 1 further comprising forming a second semiconductor fin on the substrate.
4. The method of claim 1 , wherein the stepped bottom spacer comprises a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.
5. The method of claim 1 , wherein forming the stepped gate comprises depositing a first conductive material over the stepped bottom spacer.
6. The method of claim 5 , wherein forming the stepped gate further comprises recessing the first conductive material such that the first conductive material is confined to a trench positioned over the near-channel region of the stepped bottom spacer.
7. The method of claim 6 , wherein forming the stepped gate further comprises recessing the non-channel region of the stepped bottom spacer to expose a sidewall of the first conductive material.
8. The method of claim 7 , wherein forming the stepped gate further comprises depositing a second conductive material on the recessed surface of the non-channel region of the stepped bottom spacer.
9. The method of claim 8 , wherein the stepped top spacer is formed on the first conductive material and the second conductive material.
10. A semiconductor device comprising:
a semiconductor fin on a substrate;
a stepped bottom spacer on a surface of the substrate, the stepped bottom spacer comprising a near-channel region and a non-channel region, wherein the near-channel region comprises a greater thickness than the non-channel region;
a stepped gate over a channel region of the semiconductor fin, the stepped gate comprising a first portion positioned on the near-channel region of the stepped bottom spacer and a second portion positioned on the non-channel region of the stepped bottom spacer; and
a stepped top spacer on the stepped gate.
11. The semiconductor device of claim 10 , wherein the near-channel region of the stepped bottom spacer is positioned between the non-channel region of the stepped bottom spacer and a sidewall of the semiconductor fin.
12. The semiconductor device of claim 10 further comprising a second semiconductor fin on the substrate.
13. The semiconductor device of claim 10 , wherein the stepped bottom spacer comprises a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.