Semiconductor device
A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.
1. A semiconductor device, comprising:
a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and
a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer, wherein
the gate insulator film is a single layer of a threshold value control layer that includes an oxynitride film,
the threshold value control layer is in contact with each of the gate electrode and the nitride semiconductor layer,
a nitrogen content in the threshold value control layer decreases from the nitride semiconductor layer toward the gate electrode, and
a nitrogen composition ratio of the threshold value control layer is 7 at. % around an interface between the threshold value control layer and the nitride semiconductor layer, and is 3 at. % around an interface between the threshold value control layer and the gate electrode.
2. The semiconductor device according to claim 1 , wherein
the threshold value control layer contains aluminum.
3. The semiconductor device according to claim 1 , wherein
the threshold value control layer is amorphous or microcrystalline.
4. The semiconductor device according to claim 1 , wherein
the gate insulator film further includes a first insulation layer that is stacked on the threshold value control layer at a side of the gate electrode and includes one of an oxide film, a nitride film, or an oxynitride film.
5. The semiconductor device according to claim 1 , wherein
the gate insulator film further includes a second insulation layer that is stacked on the threshold value control layer at a side of the nitride semiconductor layer and includes one of an oxide film, a nitride film, or an oxynitride film.
6. The semiconductor device according to claim 1 , wherein
the gate insulator film further includes:
a first insulation layer that is stacked on the threshold value control layer at a side of the gate electrode and includes one of an oxide film, a nitride film, or an oxynitride film; and
a second insulation layer that is stacked on the threshold value control layer at a side of the nitride semiconductor layer and includes one of an oxide film, a nitride film, or an oxynitride film.
7. The semiconductor device according to claim 1 , wherein
the nitride semiconductor layer has a stacked structure of GaN and Al x Ga 1−x N, where 0≤x≤1.
8. The semiconductor device according to claim 1 , wherein
a gate recess is disposed in the nitride semiconductor layer.
9. The semiconductor device according to claim 8 , wherein
the nitride semiconductor layer includes:
a first nitride semiconductor layer; and
a second nitride semiconductor layer that is stacked on the first nitride semiconductor layer at a side of the gate electrode and includes the gate recess, and
the first nitride semiconductor layer includes a recess that is disposed at a position overlapping the gate recess in the plan view and is recessed from the gate electrode toward the nitride semiconductor layer.
10. The semiconductor device according to claim 9 , wherein
the second nitride semiconductor layer has a uniform film thickness along an inner surface of the recess.
11. The semiconductor device according to claim 1 , further comprising:
a spacer layer disposed between the nitride semiconductor layer and the gate insulator film, wherein
the spacer layer is located between the gate electrode and the source electrode and between the gate electrode and the drain electrode in the plan view.
12. The semiconductor device according to claim 11 , wherein
a portion of the spacer layer overlaps the gate electrode in the plan view.
13. The semiconductor device according to claim 1 , wherein
the gate insulator film is not disposed in at least a portion between the gate electrode and the source electrode and between the gate electrode and the drain electrode in the plan view.
14. The semiconductor device according to claim 3 , wherein
the gate insulator film further includes a first insulation layer that is stacked on the threshold value control layer at a side of the gate electrode and includes one of an oxide film, a nitride film, or an oxynitride film.