IP Library Granted Patent US 12,477,771
Granted Patent B2
US 12,477,771 · App. 18/848,769 · Granted Nov 18, 2025

Semiconductor device

Inventors: Yusuke Kanda (Toyama, JP); Jun Shimizu (Toyama, JP)
Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
H10D30/475H10D62/8503H10D64/251H10D64/602
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Quick Facts
Patent No.
US 12,477,771
App. No.
18/848,769
Granted
Nov 18, 2025
Kind
B2
Abstract

A semiconductor device includes a substrate, a back-barrier layer, a channel layer that has a band gap smaller than a band gap of the back-barrier layer, a first barrier layer that has a band gap larger than the band gap of the channel layer, a second barrier layer that is provided to fill a first recessed portion and has a band gap larger than the band gap of the channel layer, a source electrode, a drain electrode, and a gate electrode. An In composition ratio of the first barrier layer is greater than or equal to 0 and less than an In composition ratio of the second barrier layer. An Al composition ratio of the first barrier layer is greater than or equal to an Al composition ratio of the second barrier layer.

Claims (42)

1 . A semiconductor device comprising:

a substrate;

a back-barrier layer that is provided above the substrate and includes a group-III nitride semiconductor;

a channel layer that is provided above the back-barrier layer, includes a gallium nitride semiconductor, and has a band gap smaller than a band gap of the back-barrier layer;

a first barrier layer that is provided above the channel layer, includes a group-III nitride semiconductor containing Al, and has a band gap larger than the band gap of the channel layer;

a second barrier layer that is provided to fill a first recessed portion provided in an upper face of the channel layer, includes a group-III nitride semiconductor containing Al, and has a band gap larger than the band gap of the channel layer;

a two-dimensional electron gas that is generated on a channel layer side of an interface between the channel layer and the first barrier layer or the second barrier layer;

a source electrode and a drain electrode that are provided above the first barrier layer, spaced apart from each other, and each electrically connected to the two-dimensional electron gas; and

a gate electrode that is provided above the second barrier layer and spaced apart from the source electrode and the drain electrode, wherein:

an In composition ratio of the first barrier layer is greater than or equal to 0 and less than an In composition ratio of the second barrier layer,

the In composition ratio of the first barrier layer is represented by a ratio of a total number of In atoms to a total number of all of group-III elements included in the first barrier layer,

the In composition ratio of the second barrier layer is represented by a ratio of a total number of In atoms to a total number of all of group-III elements included in the second barrier layer,

an Al composition ratio of the first barrier layer is greater than or equal to an Al composition ratio of the second barrier layers,

the Al composition ratio of the first barrier layer is represented by a ratio of a total number of Al atoms to the total number of all of the group-III elements included in the first barrier layer,

the Al composition ratio of the second barrier layer is represented by a ratio of a total number of Al atoms to the total number of all of the group-III elements included in the second barrier layer, and

the first barrier layer covers and is in direct contact with at least part of an upper face of the second barrier layer, which is opposite to a lower face of the second barrier layer facing the upper face of the channel layer.

2 . The semiconductor device according to claim 1 , wherein

a second recessed portion is provided in an upper face of the first barrier layer below the gate electrode, and

the gate electrode is in contact with a bottom face of the second recessed portion.

3 . The semiconductor device according to claim 2 , wherein

the second recessed portion penetrates the first barrier layer, and

the gate electrode is in contact with the second barrier layer.

4 . The semiconductor device according to claim 1 , wherein

the second barrier layer protrudes, by a first length, from a drain electrode-side end of the gate electrode toward a drain electrode side.

5 . The semiconductor device according to claim 4 , wherein

in the plan view, the second barrier layer protrudes, by a second length that is limited, from a source electrode-side end of the gate electrode toward a source electrode side, and

the first length is longer than the second length.

6 . The semiconductor device according to claim 1 , wherein

in a plan view of the substrate, the gate electrode protrudes from a source electrode-side end of the second barrier layer toward a source electrode side.

7 . The semiconductor device according to claim 6 , wherein

in the plan view, the gate electrode protrudes from a drain electrode-side end of the second barrier layer toward a drain electrode side.

8 . The semiconductor device according to claim 4 , wherein

in the plan view, a thickness of the second barrier layer is thicker at a position of the drain electrode-side end of the gate electrode than at a position of the source electrode-side end of the gate electrode.

9 . The semiconductor device according to claim 4 , wherein

a source electrode-side lateral face or a drain electrode-side lateral face of the second barrier layer is sloped to cause a space between the source electrode-side lateral face or the drain electrode-side lateral face and a lower face of the first barrier layer to increase from an end portion toward a central portion of the second barrier layer, and

an angle between the source electrode-side lateral face or the drain electrode-side lateral face and the lower face is an acute angle.

10 . The semiconductor device according to claim 1 , wherein

the first barrier layer includes a plurality of layers including a spacer layer as a lowest layer, and

the spacer layer has a band gap larger than a band gap of any one of the plurality of layers other than the spacer layer in the first barrier layer.

11 . The semiconductor device according to claim 10 , wherein

a third recessed portion is provided in an upper face of the first barrier layer below the gate electrode, and extends to the spacer layer, and

the gate electrode is in contact with a bottom face of the third recessed portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2024
From: KANDA, YUSUKE; SHIMIZU, JUN
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 068765/0901 →
Continuity (2)
Provisional Application 63323736 · Mar 25, 2022
Related Publication 20250113526A1 · Apr 3, 2025
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