Super junction gated AlGaN GaN HEMT
View Patent ↗Devices and methods of a transistor device including a source and a drain, the source and drain are at a horizontal plane at a location along a vertical direction. A gate, that is at a higher horizontal plane along the vertical direction then the source and drain horizontal plane. A first region under the source and drain horizontal plane, includes a first three Nitride (III-N) layer, a second III-N layer over the first III-N layer. A second region under the gate, includes a first III-N layer, a second III-N layer over the first III-N layer, and a third III-N layer over the second III-N layer. The third III-N layer at selective locations extends through the second III-N layer and into a portion of the first III-N layer along a width of the transistor. The third III-N layer is doped P-type, and the first and second III-N layers are unintentionally doped.
1. A field effect transistor (FET), comprising:
a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the FET;
a gate, such that the gate is at a second horizontal plane of the FET, wherein the second horizontal plane is higher than the first horizontal plane;
a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; and
a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction perpendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
2. The field effect transistor of claim 1 ,
wherein the first region includes
a first portion of a base layer,
a first portion of a buffer layer over the first portion of the base layer, wherein the first three Nitride (III-N) layer is over the first portion of the buffer layer, and
wherein the second region under the gate includes
a second portion of the base layer,
a second portion of the buffer layer over the second portion of the base layer, wherein the first three Nitride (III-N) layer is over the second portion of the buffer layer.
3. The field effect transistor of claim 1 , wherein the second III-N layer is an Al x In y Ga 1-x-y N, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1), wherein the first III-N layer and the third III-N layer are Gallium Nitride (GaN).
4. The field effect transistor of claim 1 , wherein the second III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the first III-N layer.
5. The field effect transistor of claim 1 , wherein a vertical thickness of the first III-N layer is greater than a vertical thickness of the second III-N layer.
6. The field effect transistor of claim 1 , wherein a vertical thickness of the first III-N layer is 10× times thicker than a vertical thickness of the second III-N layer, or the vertical thickness of the first III-N layer is 1000% percent thicker than the vertical thickness of the second III-N layer.
7. The field effect transistor of claim 1 , wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
8. The field effect transistor of claim 1 , wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
9. The field effect transistor of claim 1 , wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
10. The field effect transistor of claim 9 , wherein each profile of the plurality of profiles is equally spaced along a width of the field effect transistor.
11. The field effect transistor of claim 9 , wherein each profile of the plurality of profiles is unequally spaced and is varied along a width of the field effect transistor.
12. The field effect transistor of claim 9 , wherein the plurality of profiles at the selected locations are arranged at an angle from a vertical direction at a range from 100 degrees to 80 degrees.
13. The field effect transistor of claim 1 , wherein at an interface of the first and second III-N layers there is an accumulation of two-dimensional electron gas (2-DEG).
14. The field effect transistor of claim 13 , wherein the accumulation of the 2-DEG is depleted by the third III-N layer, resulting an enhancement-mode (E-mode) operation for the field effect transistor.
15. The field effect transistor of claim 1 , wherein the first III-N layer has a first band gap and the second III-N layer has a second band gap, such that the second bandgap of the second III-N layer is larger than the first bandgap of the first III-N layer.
16. A transistor, comprising:
a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor;
a gate, wherein the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane;
a first region under the first horizontal plane, such that the first region includes a first portion of a base substrate layer, a first portion of a buffer layer over the first portion of the base substrate layer, a first three Nitride (III-N) layer over the first portion of the buffer layer and a second III-N layer over the first III-N layer, wherein the second III-N layer has a first spontaneous polarization charge higher than a second spontaneous polarization charge of the first III-N layer, and wherein the first horizontal plane is arranged above a top surface of the second III-N layer;
a second region under the gate, such that the second region includes a second portion of the base substrate layer, a second portion of the buffer layer over the second portion of the base substrate layer, the first III-N layer over the second portion of the buffer layer, and the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction perpendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
17. The transistor of claim 16 , wherein the first III-N layer, second III-N layer and third III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD).
18. The transistor of claim 16 , wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
19. A transistor, comprising:
a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor;
a gate, such that the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane, and wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the transistor;
a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer;
a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction perpendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
20. The transistor of claim 19 , wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.