Gate structures in semiconductor devices
A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
1. A method comprising:
depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin;
depositing an n-type work function metal layer over the high-k gate dielectric layer, the n-type work function metal layer comprising aluminum and being deposited to have a same material composition throughout;
performing a passivation treatment to implant a passivating species into the high-k gate dielectric layer through the n-type work function metal layer, wherein the passivation treatment comprises a remote plasma process, wherein the passivation treatment is directly applied to an aluminum compound of the n-type work function metal layer, wherein the passivation treatment forms a passivated region comprising the passivating species in the high-k gate dielectric layer and the n-type work function metal layer, and wherein a ratio of a first average thickness of the passivated region on the sidewalls of the semiconductor fin to a second average thickness of the passivated region on a top surface of the semiconductor fin is in a range of 0.8:1 to 0.9:1; and
depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer, the metal gate stack comprising the n-type work function metal layer and the fill metal.
2. The method of claim 1 , wherein the remote plasma process comprises exposing the high-k gate dielectric layer to radicals.
3. The method of claim 2 , wherein the radicals are fluorine radicals, nitrogen radicals, or a combination thereof.
4. The method of claim 2 , wherein the passivation treatment comprises using the aluminum to attract the radicals into the high-k gate dielectric layer.
5. The method of claim 1 , wherein depositing the high-k gate dielectric layer comprises depositing the high-k gate dielectric layer comprising oxygen vacancies, dangling bonds, or a combination thereof.
6. The method of claim 5 , wherein the passivating treatment provides the passivating species in the high-k gate dielectric layer to fill the oxygen vacancies, terminate the dangling bonds, or a combination thereof.
7. The method of claim 1 further comprising:
depositing an adhesion layer between the high-k gate dielectric layer and the n-type work function metal layer.
8. The method of claim 1 further comprising depositing a barrier layer between the n-type work function metal layer and the fill metal.
9. The method of claim 1 further comprising depositing a p-type work function metal layer between the high-k gate dielectric layer and the n-type work function metal layer.
10. The method of claim 1 , depositing the fill metal over the n-type work function metal layer comprises depositing the fill metal over the n-type work function metal layer after the passivation treatment.
11. A method comprising:
forming a semiconductor fin extending above an isolation region in a semiconductor device;
depositing a high-k gate dielectric layer over and along sidewalls of the semiconductor fin, the high-k gate dielectric layer comprising deposition defects;
depositing a first work function metal layer over the high-k gate dielectric layer, wherein the first work function metal layer comprises an n-type metal;
depositing a capping layer over the first work function metal layer, wherein the capping layer comprises the n-type metal, wherein a concentration of the n-type metal in the capping layer decreases in a direction away from the first work function metal layer;
introducing a passivating species into the high-k gate dielectric layer through the first work function metal layer, wherein introducing the passivating species comprises:
generating a plasma;
filtering the plasma to provide radicals from an afterglow of the plasma, wherein the semiconductor device is exposed to the radicals; and
after introducing the passivating species, depositing fill metal over the first work function metal layer.
12. The method of claim 11 , wherein generating the plasma comprises generating the plasma from a precursor gas comprising fluorine, nitrogen, or a combination thereof.
13. The method of claim 11 further comprising forming a second work function metal layer between the high-k gate dielectric layer and the first work function metal layer, wherein the second work function metal layer is a p-type work function metal layer.
14. The method of claim 11 , wherein introducing the passivating species into the high-k gate dielectric layer through the first work function metal layer comprises using the n-type metal of the first work function metal layer to attract the radicals.
15. The method of claim 11 , wherein introducing the passivating species is performed at a temperature of less than 100° C.
16. The method of claim 11 , wherein the radicals are fluorine radicals, nitrogen radicals, or a combination thereof.
17. A method comprising:
depositing a high-k gate dielectric layer over and extending along sidewalls of a semiconductor fin;
forming a gate stack over and along sidewalls of the high-k gate dielectric layer, wherein depositing the gate stack comprises:
depositing a first work function metal layer comprising an n-type metal;
depositing a capping layer over the first work function metal layer, wherein the capping layer comprises the n-type metal, and wherein a concentration of the n-type metal in the capping layer decreases in a direction away from the first work function metal layer;
performing a fluorination treatment on the high-k gate dielectric layer through the first work function metal layer; and
depositing a first fill metal layer over the first work function metal layer wherein the first fill metal layer is free of fluorine.
18. The method of claim 17 , wherein forming the gate stack further comprises:
depositing an adhesion layer over the high-k dielectric gate layer prior to depositing the first work function metal layer;
depositing a barrier layer over the capping layer prior to depositing the first fill metal layer; and
depositing a second fill metal layer over the first fill metal layer, wherein the second fill metal layer comprises fluorine.
19. The method of claim 17 , wherein after performing the fluorination treatment:
a fluorine concentration of a portion of the high-k gate dielectric layer on a top surface of the semiconductor fin is in a range of 1.0 at % to 40.0 at %; and
a fluorine concentration of a portion of the high-k gate dielectric layer on a sidewall of the semiconductor fin is in a range of 1.0 at % to 40.0 at %.
20. The method of claim 17 , the fluorination treatment is a plasma treatment.