Switching circuit with voltage bias
In one embodiment, an RF impedance matching network for a plasma chamber is disclosed. The matching network includes an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit for switching in and out the discrete capacitor to alter a total capacitance of the EVC. Each switching circuit comprises at least one switching field-effect transistor (FET) operably coupled to the corresponding discrete capacitor to cause the switching in and out of the discrete capacitor. For each switching circuit, when the switching circuit is switched OFF to switch out the corresponding discrete capacitor, the at least one switching FET receives a bias voltage from a bias voltage source to reduce a capacitance variability of the at least one switching FET.
1. An impedance matching network comprising:
a radio frequency (RF) input operably coupled to an RF source providing an RF signal;
an RF output operably coupled to a plasma chamber; and
an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit for switching in and out the discrete capacitor to alter a total capacitance of the EVC;
wherein each switching circuit comprises at least one switching field-effect transistor (FET) operably coupled to the corresponding discrete capacitor to cause the switching in and out of the discrete capacitor;
wherein for each switching circuit, when the switching circuit is switched OFF to switch out the corresponding discrete capacitor, the at least one switching FET receives a variable bias voltage from a bias voltage source to reduce a capacitance variability of the at least one switching FET; and
wherein the bias voltage is varied based on a measured value of the RF signal to keep an offset at or slightly above a desired bias voltage.
2. The matching network of claim 1 wherein each switching circuit further comprises a blocking element positioned between the bias voltage source and the at least one switching FET, the blocking element blocking an RF current and passing the bias voltage.
3. The matching network of claim 2 wherein the blocking element comprises an inductor, a diode, or a resistor.
4. The matching network of claim 1 wherein the at least one switching FET comprises a first switching FET and a second switching FET coupled in series.
5. The matching network of claim 4 wherein either:
a drain of the first switching FET and a drain of the second switching FET are coupled to a common node, the common node receiving the bias voltage; or
a source of the first switching FET and a source of the second switching FET are coupled to a common node, the common node receiving the bias voltage.
6. The matching network of claim 1 further comprising a blocking inductor positioned between the bias voltage source and the switching circuits, the blocking inductor blocking an RF current from returning to the bias voltage source.
7. The matching network of claim 1 wherein each switching circuit further comprises at least one biasing FET positioned between the bias voltage source and the at least one switching FET, the biasing FET providing the voltage bias to the at least one switching FET.
8. A method of matching an impedance comprising:
coupling an RF input of a matching network to an RF source providing an RF signal;
coupling an RF output of the matching network to a plasma chamber, wherein the matching network comprises an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit configured to switch in and out the discrete capacitor, wherein each switching circuit comprises at least one switching field-effect transistor (FET) operably coupled to the corresponding discrete capacitor to cause the switching in and out of the discrete capacitor;
for each switching circuit, when the switching circuit is switched OFF to switch out the corresponding discrete capacitor, the at least one switching FET receiving a bias voltage from a bias voltage source to reduce a capacitance variability of the at least one switching FET, the bias voltage being varied based on a measured value of the RF signal to keep an offset at or slightly above a desired bias voltage; and
matching an impedance by at least one of the switching circuits of the EVC switching in or out its corresponding discrete capacitor to alter a total capacitance of the EVC.
9. The method of claim 8 wherein each switching circuit further comprises a blocking element positioned between the bias voltage source and the at least one switching FET, the blocking element blocking an RF current and passing the bias voltage.
10. The method of claim 9 wherein the blocking element comprises an inductor, a diode, or a resistor.
11. The method of claim 8 wherein the at least one switching FET comprises a first switching FET and a second switching FET coupled in series.
12. The method of claim 11 wherein either:
a drain of the first switching FET and a drain of the second switching FET are coupled to a common node, the common node receiving the bias voltage; or
a source of the first switching FET and a source of the second switching FET are coupled to a common node, the common node receiving the bias voltage.
13. The method of claim 8 wherein the measured value of the RF signal is a measured RF peak voltage of the RF signal.
14. The method of claim 13 wherein the bias voltage is varied such that, as the RF peak voltage increased, the bias voltage is decreased.
15. The method of claim 8 wherein the at least one switching FET receives the bias voltage at a drain of the at least one switching FET.
16. The method of claim 8 wherein the at least one switching FET receives the bias voltage at a source of the at least one switching FET.
17. The method of claim 8 further comprising a blocking inductor positioned between the bias voltage source and the switching circuits, the blocking inductor blocking an RF current from returning to the bias voltage source.
18. The method of claim 8 wherein each switching circuit further comprises at least one biasing FET positioned between the bias voltage source and the at least one switching FET, the biasing FET providing the voltage bias to the at least one switching FET.
19. A semiconductor processing tool comprising:
a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and
an impedance matching network operably coupled to the plasma chamber, the matching network comprising:
an RF input operably coupled to an RF source providing an RF signal;
an RF output operably coupled to the plasma chamber; and
an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit for switching in and out the discrete capacitor to alter a total capacitance of the EVC;
wherein each switching circuit comprises at least one switching field-effect transistor (FET) operably coupled to the corresponding discrete capacitor to cause the switching in and out of the discrete capacitor;
wherein for each switching circuit, when the switching circuit is switched OFF to switch out the corresponding discrete capacitor, the at least one switching FET receives a bias voltage from a bias voltage source to reduce a capacitance variability of the at least one switching FET; and
wherein the bias voltage is varied based on a measured value of the RF signal to keep an offset at or slightly above a desired bias voltage.
20. A method of fabricating a semiconductor, the method comprising:
placing a substrate in a plasma chamber configured to deposit a material layer on the substrate or etch a material layer from the substrate;
energizing plasma within the plasma chamber by providing an RF signal from an RF source to the plasma chamber to perform the deposition or etching; and
while energizing the plasma, carrying out an impedance match by an impedance matching network coupled between the plasma chamber and the RF source, the matching network comprising:
an RF input operably coupled to the RF source;
an RF output operably coupled to the plasma chamber; and
an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit for switching in and out the discrete capacitor to alter a total capacitance of the EVC;
wherein each switching circuit comprises at least one switching field-effect transistor (FET) operably coupled to the corresponding discrete capacitor to cause the switching in and out of the discrete capacitor;
wherein for each switching circuit, when the switching circuit is switched OFF to switch out the corresponding discrete capacitor, the at least one switching FET receives a bias voltage from a bias voltage source to reduce a capacitance variability of the at least one switching FET; and
wherein the bias voltage is varied based on a measured value of the RF signal to keep an offset at or slightly above a desired bias voltage.