Granted Patent B2

US 11,398,493 · App. 16/736,297 · Granted Jul 26, 2022

Inventor: Theodore T. Pekny (Sunnyvale, CA)

Assignee: Micron Technology, Inc.

H01L27/11582H01L27/1157H01L27/11556H01L27/11565H01L27/11568H01L27/11578H01L29/0649H01L29/40117

Abstract

Claims (115)

1. An array of memory cells, comprising:

a first memory cell and a second memory cell having respective control gates electrically connected to a first access line, and having respective charge storage nodes;

a third memory cell and a fourth memory cell having respective control gates electrically connected to a second access line, and having respective charge storage nodes; and

an isolation region between the first access line and the second access line;

wherein the charge storage node of the first memory cell, the charge storage node of the second memory cell, the charge storage node of the third memory cell, and the charge storage node of the fourth memory cell are each between the first access line and the second access line, and are each in contact with the isolation region;

wherein an area of contact between the charge storage node of the first memory cell and the isolation region, and an area of contact between the charge storage node of the second memory cell and the isolation region, are both on a first side of the isolation region; and

wherein an area of contact between the charge storage node of the third memory cell and the isolation region, and an area of contact between the charge storage node of the fourth memory cell and the isolation region, are both on a second side of the isolation region opposite the first side of the isolation region.

2. The array of memory cells of claim 1 , wherein no portion of the charge storage node of the first memory cell is in contact with any portion of the charge storage node of the third memory cell.

3. The array of memory cells of claim 1 , wherein the charge storage node of the first memory cell is an oxide-nitride-oxide structure.

4. The array of memory cells of claim 1 , further comprising a first contiguous semiconductor structure forming channels for both the first memory cell and the third memory cell, and a second contiguous semiconductor structure forming channels for both the second memory cell and the fourth memory cell.

5. An array of memory cells, comprising:

a first memory cell and a second memory cell having respective control gates connected to a first access line, and having respective charge storage nodes;

a third memory cell and a fourth memory cell having respective control gates connected to a second access line, and having respective charge storage nodes;

an isolation region between the first access line and the second access line;

a first contiguous semiconductor structure forming channels for both the first memory cell and the third memory cell; and

a second contiguous semiconductor structure forming channels for both the second memory cell and the fourth memory cell;

wherein the charge storage node of the first memory cell, the charge storage node of the second memory cell, the charge storage node of the third memory cell, and the charge storage node of the fourth memory cell are each between the first access line and the second access line, and are each in contact with the isolation region;

wherein an area of the charge storage node of the first memory cell in contact with the first access line is greater than an area of the charge storage node of the first memory cell in contact with the first contiguous semiconductor structure;

wherein an area of the charge storage node of the second memory cell in contact with the first access line is greater than an area of the charge storage node of the second memory cell in contact with the second contiguous semiconductor structure;

wherein an area of the charge storage node of the third memory cell in contact with the second access line is greater than an area of the charge storage node of the third memory cell in contact with the first contiguous semiconductor structure; and

wherein an area of the charge storage node of the fourth memory cell in contact with the second access line is greater than an area of the charge storage node of the fourth memory cell in contact with the second contiguous semiconductor structure.

6. The array of memory cells of claim 1 , wherein a portion of the charge storage node of the first memory cell is parallel with a portion of the charge storage node of the third memory cell.

7. An array of memory cells, comprising:

a first memory cell and a second memory cell having respective control gates connected to a first access line, and having respective charge storage nodes;

a third memory cell and a fourth memory cell having respective control gates connected to a second access line, and having respective charge storage nodes;

a fifth memory cell and a sixth memory cell having respective control gates connected to the second access line, and having respective charge storage nodes; and

an isolation region between the first access line and the second access line;

wherein the charge storage node of the first memory cell, the charge storage node of the second memory cell, the charge storage node of the third memory cell, and the charge storage node of the fourth memory cell are each between the first access line and the second access line, and are each in contact with the isolation region;

wherein the second access line is between the charge storage node of the fifth memory cell and the charge storage node of the third memory cell; and

wherein the second access line is between the charge storage node of the sixth memory cell and the charge storage node of the fourth memory cell.

8. The array of memory cells of claim 7 , wherein the isolation region is a first isolation region, the array of memory cells further comprising:

a seventh memory cell and an eighth memory cell having respective control gates connected to a third access line, and having respective charge storage nodes; and

a second isolation region between the second access line and the third access line;

wherein the charge storage node of the fifth memory cell, the charge storage node of the sixth memory cell, the charge storage node of the seventh memory cell, and the charge storage node of the eighth memory cell are each between the second access line and the third access line, and are each in contact with the second isolation region.

9. An array of memory cells, comprising:

a plurality of memory cells comprising a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, wherein each memory cell of the plurality of memory cells comprises a control gate, a charge storage node and a channel;

wherein the control gate of the first memory cell and the control gate of the second memory cell are commonly electrically connected to a first access line;

wherein the control gate of the third memory cell and the control gate of the fourth memory cell are commonly electrically connected to a second access line;

wherein the charge storage node of the first memory cell and the charge storage node of the second memory cell are each between the first access line and the second access line;

wherein the charge storage node of the third memory cell is between the second access line and the charge storage node of the first memory cell;

wherein the charge storage node of the fourth memory cell is between the second access line and the charge storage node of the second memory cell;

wherein the charge storage node of the first memory cell is electrically isolated from the charge storage node of the third memory cell by an isolation region;

wherein the charge storage node of the second memory cell is electrically isolated from the charge storage node of the fourth memory cell by the isolation region;

wherein no portion of the isolation region is located between two different portions of the first access line; and

wherein no portion of the isolation region is located between two different portions of the second access line.

10. The array of memory cells of claim 9 , wherein the charge storage node of the first memory cell is separated from the charge storage node of the second memory cell, and wherein the charge storage node of the third memory cell is separated from the charge storage node of the fourth memory cell.

11. The array of memory cells of claim 9 , wherein the first memory cell, the second memory cell, the third memory cell and the fourth memory cell are all formed at a same level relative to a semiconductor substrate.

12. The array of memory cells of claim 9 , wherein the charge storage node of the first memory cell comprises a first dielectric material in contact with the first access line, a second dielectric material in contact with the first dielectric material, and a third dielectric material in contact with the second dielectric material.

13. The array of memory cells of claim 12 , wherein the first dielectric material and the third dielectric material each comprise silicon dioxide, and wherein the second dielectric material comprises silicon nitride.

14. An array of memory cells, comprising:

a plurality of memory cells comprising a first memory cell, a second memory cell, a third memory cell, a fourth memory cell, a fifth memory cell, a sixth memory cell, a seventh memory cell, and an eighth memory cell, wherein each memory cell of the plurality of memory cells comprises a control gate, a charge storage node and a channel;

a first access line;

a second access line;

a third access line;

a fourth access line;

a first semiconductor structure; and

a second semiconductor structure;

wherein the control gate of the first memory cell and the control gate of the second memory cell are commonly connected to the first access line;

wherein the control gate of the third memory cell and the control gate of the fourth memory cell are commonly connected to the second access line;

wherein the control gate of the fifth memory cell and the control gate of the sixth memory cell are commonly connected to the third access line;

wherein the control gate of the seventh memory cell and the control gate of the eighth memory cell are commonly connected to the fourth access line;

wherein the charge storage node of the first memory cell and the charge storage node of the second memory cell are each between the first access line and the second access line;

wherein the charge storage node of the third memory cell is between the second access line and the charge storage node of the first memory cell;

wherein the charge storage node of the fourth memory cell is between the second access line and the charge storage node of the second memory cell;

wherein the charge storage node of the first memory cell is electrically isolated from the charge storage node of the third memory cell;

wherein the charge storage node of the second memory cell is electrically isolated from the charge storage node of the fourth memory cell;

wherein the charge storage node of the fifth memory cell and the charge storage node of the sixth memory cell are each between the third access line and the fourth access line;

wherein the charge storage node of the seventh memory cell is between the fourth access line and the charge storage node of the fifth memory cell;

wherein the charge storage node of the eighth memory cell is between the fourth access line and the charge storage node of the sixth memory cell;

wherein the charge storage node of the fifth memory cell is electrically isolated from the charge storage node of the seventh memory cell;

wherein the charge storage node of the sixth memory cell is electrically isolated from the charge storage node of the eighth memory cell;

wherein the charge storage node of the first memory cell is contiguous with the charge storage node of the fifth memory cell;

wherein the charge storage node of the second memory cell is contiguous with the charge storage node of the sixth memory cell;

wherein the charge storage node of the third memory cell is contiguous with the charge storage node of the seventh memory cell; and

wherein the charge storage node of the fourth memory cell is contiguous with the charge storage node of the eighth memory cell.

15. An array of memory cells, comprising:

a plurality of memory cells comprising a first memory cell, a second memory cell, a third memory cell, a fourth memory cell, a fifth memory cell, a sixth memory cell, a seventh memory cell, and an eighth memory cell, wherein each memory cell of the plurality of memory cells comprises a control gate, a charge storage node and a channel;

a first access line;

a second access line;

a third access line;

a first isolation region between the first access line and the second access line; and

a second isolation region between the second access line and the third access line;

wherein the control gate of the first memory cell and the control gate of the second memory cell are commonly connected to the first access line;

wherein the control gate of the third memory cell and the control gate of the fourth memory cell are commonly connected to the second access line;

wherein the control gate of the fifth memory cell and the control gate of the sixth memory cell are commonly connected to the second access line;

wherein the control gate of the seventh memory cell and the control gate of the eighth memory cell are commonly connected to the third access line;

wherein the charge storage node of the first memory cell and the charge storage node of the second memory cell are each between the first access line and the second access line;

wherein the charge storage node of the third memory cell is between the second access line and the charge storage node of the first memory cell;

wherein the charge storage node of the fourth memory cell is between the second access line and the charge storage node of the second memory cell;

wherein the charge storage node of the first memory cell is electrically isolated from the charge storage node of the third memory cell by the first isolation region;

wherein the charge storage node of the second memory cell is electrically isolated from the charge storage node of the fourth memory cell by the first isolation region;

wherein the second access line is between the charge storage node of the fifth memory cell and the charge storage node of the third memory cell;

wherein the second access line is between the charge storage node of the sixth memory cell and the charge storage node of the fourth memory cell;

wherein the first memory cell is selectively connected to a first data line;

wherein the second memory cell is selectively connected to a second data line;

wherein the seventh memory cell is selectively connected to the first data line; and

wherein the eighth memory cell is selectively connected to the second data line.

16. The array of memory cells of claim 15 , wherein the third memory cell is selectively connected to the first data line, wherein the fourth memory cell is selectively connected to the second data line, wherein the fifth memory cell is selectively connected to the first data line, and wherein the sixth memory cell is selectively connected to the second data line.

17. An array of memory cells, comprising:

a plurality of memory cells formed overlying a semiconductor substrate, wherein the plurality of memory cells comprises a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, wherein each memory cell of the plurality of memory cells comprises a control gate, a charge storage node and a channel;

wherein the control gate of the first memory cell is connected to a first access line at a first level relative to the semiconductor substrate;

wherein the control gate of the second memory cell is connected to a second access line at the first level relative to the semiconductor substrate;

wherein the control gate of the third memory cell is connected to a third access line at a second level relative to the semiconductor substrate, different than the first level;

wherein the control gate of the fourth memory cell is connected to a fourth access line at the second level relative to the semiconductor substrate;

wherein the charge storage node of the first memory cell and the charge storage node of the second memory cell are each between the first access line and the second access line;

wherein the charge storage node of the third memory cell and the charge storage node of the fourth memory cell are each between the third access line and the fourth access line;

wherein the charge storage node of the second memory cell is between the second access line and the charge storage node of the first memory cell;

wherein the charge storage node of the fourth memory cell is between the fourth access line and the charge storage node of the third memory cell;

wherein the charge storage node of the first memory cell is contiguous with the charge storage node of the third memory cell; and

wherein the charge storage node of the second memory cell is contiguous with the charge storage node of the fourth memory cell.

18. The array of memory cells of claim 17 , further comprising:

an isolation region;

wherein the charge storage node of the first memory cell, the charge storage node of the second memory cell, the charge storage node of the third memory cell, and the charge storage node of the fourth memory cell are each in contact with the isolation region.

19. The array of memory cells of claim 18 , wherein no portion of the charge storage node of the first memory cell is in contact with the charge storage node of the second memory cell, and wherein no portion of the charge storage node of the third memory cell is in contact with the charge storage node of the fourth memory cell.

20. The array of memory cells of claim 17 , wherein a distance between a center of the charge storage node of the first memory cell and a center of the charge storage node of the second memory cell is greater than a distance between a center of the charge storage node of the third memory cell and a center of the charge storage node of the fourth memory cell.

Continuity (8)