Integration methods to fabricate internal spacers for nanowire devices
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
1. An integrated circuit structure, comprising:
a nanowire above a substrate;
a first gate structure wrapped around the nanowire, the first gate structure having a first sidewall and a second sidewall opposite the first sidewall;
a first channel region in the nanowire and surrounded by the first gate structure;
a first internal insulative spacer adjacent to a portion of the first sidewall of the first gate structure below the nanowire;
a second internal insulative spacer adjacent to a portion of the second sidewall of the first gate structure below the nanowire;
a second gate structure wrapped around the nanowire, the second gate structure having a first sidewall and a second sidewall opposite the first sidewall;
a second channel region in the nanowire and surrounded by the second gate structure;
a third internal insulative spacer adjacent to a portion of the first sidewall of the second gate structure below the nanowire;
a fourth internal insulative spacer adjacent to a portion of the second sidewall of the second gate structure below the nanowire;
a first source or drain region on a first side of the first channel region;
a second source or drain region on a second side of the first channel region opposite the first side, and the second source or drain region on a first side of the second channel region; and
a third source or drain region on a second side of the second channel region opposite the second side.
2. The integrated circuit structure of claim 1 , further comprising:
a first external sidewall spacer adjacent to the first sidewall of the first gate structure above the nanowire;
a second external sidewall spacer adjacent to the second sidewall of the first gate structure above the nanowire;
a third external sidewall spacer adjacent to the first sidewall of the second gate structure above the nanowire;
a fourth external sidewall spacer adjacent to the second sidewall of the second gate structure above the nanowire.
3. The integrated circuit structure of claim 1 , wherein the first gate structure comprises a first gate electrode and a first gate dielectric, and wherein the second gate structure comprises a second gate electrode and a second gate dielectric.
4. The integrated circuit structure of claim 3 , wherein the first gate dielectric has a different composition than the first and second internal insulative spacers, and wherein the second gate dielectric has a different composition than the third and fourth internal insulative spacers.
5. The integrated circuit structure of claim 3 , wherein the first gate dielectric is in direct contact with the first and second internal insulative spacers, and wherein the second gate dielectric is in direct contact with the third and fourth internal insulative spacers.
6. The integrated circuit structure of claim 1 , wherein the first, second, third and fourth internal insulative spacers each comprise a dielectric material selected from the group consisting of SiN, SiO 2 , SiON, and SiC.
7. The integrated circuit structure of claim 1 , wherein the substrate is an SOI substrate.
8. The integrated circuit structure of claim 1 , further comprising first, second and third source or drain contacts in contact with the first, second and third source or drain regions, respectively.
9. The integrated circuit structure of claim 1 , wherein the nanowire is a silicon nanowire.
10. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a nanowire above a substrate;
a first gate structure wrapped around the nanowire, the first gate structure having a first sidewall and a second sidewall opposite the first sidewall;
a first channel region in the nanowire and surrounded by the first gate structure;
a first internal insulative spacer adjacent to a portion of the first sidewall of the first gate structure below the nanowire;
a second internal insulative spacer adjacent to a portion of the second sidewall of the first gate structure below the nanowire;
a second gate structure wrapped around the nanowire, the second gate structure having a first sidewall and a second sidewall opposite the first sidewall;
a second channel region in the nanowire and surrounded by the second gate structure;
a third internal insulative spacer adjacent to a portion of the first sidewall of the second gate structure below the nanowire;
a fourth internal insulative spacer adjacent to a portion of the second sidewall of the second gate structure below the nanowire;
a first source or drain region on a first side of the first channel region;
a second source or drain region on a second side of the first channel region opposite the first side, and the second source or drain region on a first side of the second channel region; and
a third source or drain region on a second side of the second channel region opposite the second side.
11. The computing device of claim 10 , further comprising:
a memory coupled to the board.
12. The computing device of claim 10 , further comprising:
a communication chip coupled to the board.
13. The computing device of claim 10 , further comprising:
a camera coupled to the board.
14. The computing device of claim 10 , wherein the component is a packaged integrated circuit die.
15. The computing device of claim 10 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16. The computing device of claim 10 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.
17. The computing device of claim 10 , wherein the first gate structure comprises a first gate electrode and a first gate dielectric, and wherein the second gate structure comprises a second gate electrode and a second gate dielectric.
18. The computing device of claim 17 , wherein the first gate dielectric has a different composition than the first and second internal insulative spacers, and wherein the second gate dielectric has a different composition than the third and fourth internal insulative spacers.
19. The computing device of claim 17 , wherein the first gate dielectric is in direct contact with the first and second internal insulative spacers, and wherein the second gate dielectric is in direct contact with the third and fourth internal insulative spacers.
20. The computing device of claim 10 , wherein the substrate is an SOI substrate.