Nanosheet transistor with self-aligned dielectric pillar
Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.
1. A method for forming a semiconductor device, the method comprising:
forming a bottom isolation structure on a substrate;
forming a nanosheet stack on the bottom isolation structure, the bottom isolation structure between the nanosheet stack and the substrate;
forming a sacrificial region over the nanosheet stack, the sacrificial region in direct contact with the bottom isolation structure;
forming a dielectric pillar adjacent to the nanosheet stack, the dielectric pillar positioned directly on a shallow trench isolation region of the substrate, the dielectric pillar in direct contact with sidewalls of the sacrificial region;
removing the sacrificial region to expose a surface of the bottom isolation structure and a surface of the shallow trench isolation region;
forming a conformal liner over a source or drain (S/D) region and the dielectric pillar;
forming an interlayer dielectric over the conformal liner;
removing a portion of the interlayer dielectric and a portion of the conformal liner to form a contact trench exposing a surface of the S/D region and a surface of the dielectric pillar; and
forming a trench silicide in the contact trench.
2. The method of claim 1 further comprising recessing the nanosheet stack to expose a surface of the shallow trench isolation region, wherein recessing the nanosheet stack comprises removing the sacrificial region.
3. The method of claim 1 , wherein the dielectric pillar serves as an etch stop while forming the contact trench.