Gate driver with serial communication
A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.
1. A device comprising:
a transistor having a gate;
an input terminal;
a serial communication interface having a control input; and
a drive circuit having a drive input and a drive output, the drive output coupled to the gate;
in which the input terminal is coupled through a first path to the drive input and through a second path to the control input, and the second path diverges from the first path.
2. The device of claim 1 , wherein the first path diverges from the second path at the input terminal.
3. The device of claim 1 , wherein the first path is independent of the second path.
4. The device of claim 1 , wherein the first path is external to the serial communication interface.
5. The device of claim 1 , wherein the second path is external to the drive circuit.
6. The device of claim 1 , wherein the input terminal is configured to receive a pulse width modulation (PWM) signal, the first path is configured to transmit the PWM signal from the input terminal to the drive input and bypass the serial communication interface.
7. The device of claim 1 , wherein the input terminal is configured to receive a pulse width modulation (PWM) signal, the first path is configured to transmit the PWM signal from the input terminal to the control input and bypass the drive circuit.
8. The device of claim 1 , wherein the serial communication interface includes:
a data input terminal configured to receive data; and
a control circuit configured to assign a value to an address register based on the data when the control circuit is initiated by a signal from the input terminal.
9. The device of claim 8 , wherein the signal has a pulse width, and the control circuit is in an address initialization mode for a duration of the pulse width.
10. The device of claim 8 , wherein the address register has a 1-to-1 correspondence with the drive circuit.
11. A traction inverter comprising:
a transistor having a gate;
an input terminal;
a drive circuit having a drive input coupled to the input terminal, and a driver output coupled to the gate; and
a serial communication interface having a control circuit configured to assign a value to an address register responsive to a signal from the input terminal.
12. The traction inverter of claim 11 , further comprising:
a data input terminal configured to receive address data,
wherein the control circuit is configured to assign the value to the address register based on the address data during an assertion period of the signal.
13. The traction inverter of claim 11 , wherein the signal has a pulse width, and the control circuit is in an address initialization mode for a duration of the pulse width.
14. The traction inverter of claim 11 , wherein the address register has a 1-to-1 correspondence with the drive circuit.
15. The traction inverter of claim 11 , wherein:
the input terminal is coupled through a first path to the drive input and through a second path to the control circuit, and the second path diverges from the first path.
16. A system comprising:
an input terminal;
a silicon carbide transistor having a gate;
a drive circuit having a drive input coupled to the input terminal and a driver output coupled to the gate; and
a serial communication interface having a control circuit configured to assign a value to an address register responsive to a signal from the input terminal.
17. The system of claim 16 , further comprising:
a data input terminal configured to receive address data,
wherein the control circuit is configured to assign the value to the address register based on the address data during an assertion period of the signal.
18. The system of claim 16 , wherein the signal has a pulse width, and the control circuit is in an address initialization mode for a duration of the pulse width.
19. The system of claim 16 , wherein the address register has a 1-to-1 correspondence with the drive circuit.
20. The system of claim 16 , wherein:
the input terminal is coupled through a first path to the drive input and through a second path to the control circuit, and the second path diverges from the first path.