Methods of manufacturing a semiconductor package
View Patent ↗A system substrate package, a system package, and methods of forming the same are described herein. The system substrate package includes an integrated substrate with multiple discrete interconnect structures. In embodiments the multiple discrete interconnect structures are placed and encapsulated and have a gap formed between the multiple discrete interconnect structures. The system substrate package reduces package warpage and mitigates board level reliability issues.
1. A method comprising:
forming a redistribution structure on a carrier;
attaching a first interconnect structure and a second interconnect structure on a first side of the redistribution structure, wherein after the attaching, a first gap is disposed between a sidewall of the first interconnect structure and a sidewall of the second interconnect structure, wherein the first gap has a first height measured from the first side of the redistribution structure to a surface of the first interconnect structure opposite the redistribution structure;
depositing a molded underfill material around the first interconnect structure, the molded underfill material having a second height within the first gap and having a third height on an opposite side of the first interconnect structure from the second interconnect structure, the second height being less than the first height and the third height, wherein the molded underfill material within the first gap is in contact with the redistribution structure; and
mounting external electrical connectors on a side of the first interconnect structure facing away from the redistribution structure and on a side of the second interconnect structure facing away from the redistribution structure, wherein the third height is greater than a distance between the respective external electrical connector and the first side of the redistribution structure.
2. The method of claim 1 , wherein the redistribution structure is part of a system package that has a size of greater than 90 mm 2 .
3. The method of claim 1 , further comprising removing the carrier and mounting a semiconductor device adjacent to a second side of the redistribution structure that is opposite the first side of the redistribution structure.
4. The method of claim 1 , wherein the attaching the first interconnect structure and the second interconnect structure comprises:
attaching the first interconnect structure; and
separately attaching the second interconnect structure.
5. The method of claim 1 , wherein the attaching the first interconnect structure and the second interconnect structure comprises:
attaching a single package interconnect structure to the redistribution structure; and
separating the single package interconnect structure into the first interconnect structure and the second interconnect structure after the attaching the single package interconnect structure.
6. The method of claim 1 , wherein the carrier is a wafer.
7. The method of claim 6 , wherein the carrier is a panel.
8. The method of claim 1 , wherein the first interconnect structure comprises a first core substrate and a first routing layer on a side of the first core substrate facing away from the redistribution structure, and the second interconnect structure comprises a second core substrate and a second routing layer on a side of the second core substrate facing away from the redistribution structure.
9. A method of manufacturing a semiconductor package, the method comprising:
placing a first interconnect structure in electrical connection to a first side of a redistribution structure, wherein the first interconnect structure comprises a first core substrate and a first routing layer on a side of the first core substrate facing away from the redistribution structure;
after placing the first interconnect structure, placing a second interconnect structure in electrical connection to the first side of the redistribution structure, wherein the second interconnect structure comprises a second core substrate and a second routing layer on a side of the second core substrate facing away from the redistribution structure, wherein the second interconnect structure is spaced apart from the first interconnect structure, wherein the first interconnect structure has a first sidewall adjacent to the second interconnect structure and a second sidewall facing away from the second interconnect structure;
placing a molded underfill material around the first interconnect structure, wherein the molded underfill material has a first surface facing away from the redistribution structure, wherein a first distance from the redistribution structure to the first surface of the molded underfill material adjacent the first sidewall of the first interconnect structure is less than a second distance from the redistribution structure to the first surface of the molded underfill material adjacent the second sidewall of the first interconnect structure; and
placing a semiconductor device in electrical connection to a second side of the redistribution structure opposite the first interconnect structure.
10. The method of claim 9 , wherein the semiconductor package is a system package.
11. The method of claim 9 , wherein after the placing the molded underfill material, the molded underfill material has a first interface with a protection layer of the first interconnect structure.
12. The method of claim 11 , wherein the molded underfill material has a second interface with the first routing layer of the first interconnect structure.
13. The method of claim 12 , wherein the molded underfill material has a third interface with the first core substrate of the first interconnect structure.
14. The method of claim 13 , wherein the molded underfill material covers all of the second sidewall.
15. A method of manufacturing a semiconductor package, the method comprising:
placing a first interconnect structure and a second interconnect structure in electrical connection to a first side of a redistribution structure, wherein the first interconnect structure comprises a first core substrate and a first routing layer on a side of the first core substrate facing away from the redistribution structure, wherein the second interconnect structure comprises a second core substrate and a second routing layer on a side of the second core substrate facing away from the redistribution structure, wherein each of the first interconnect structure and the second interconnect structure is free of active devices, wherein the first interconnect structure and the second interconnect structure is spaced apart by a gap;
placing a molded underfill material over the redistribution structure, wherein the molded underfill material covers a first sidewall of the first interconnect structure within the gap, a second sidewall of the first interconnect structure outside the gap, and a surface of the first interconnect structure adjacent the redistribution structure, wherein a height of the second sidewall covered by the molded underfill material is greater than a height of a portion of the first sidewall covered by the molded underfill material; and
mounting external electrical connectors on the first routing layer and the second routing layer.
16. The method of claim 15 , wherein the molded underfill material covers all of the second sidewall.
17. The method of claim 15 , wherein the molded underfill material has an interface with the first core substrate of the first interconnect structure.
18. The method of claim 15 , wherein a surface of the molded underfill material facing away from the redistribution structure and within the gap is spaced apart from a surface of the first core substrate facing away from the redistribution structure.
19. The method of claim 15 , further comprising mounting a semiconductor device adjacent to a second side of the redistribution structure, the second side of the redistribution structure being opposite the first side of the redistribution structure.
20. The method of claim 19 , wherein the mounting comprises:
attaching connectors over the second side of the redistribution structure; and
attaching the semiconductor device over the connectors.