Field effect transistor with controllable resistance
A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
1. A semiconductor device comprising:
a source terminal;
a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;
an energy barrier adjacent to the source terminal and the channel region; and
a conductive gate stack formed over the channel region,
wherein the energy barrier and the channel region are doped using a first dopant, and wherein the source terminal and the drain terminal are doped using a second dopant.
2. The semiconductor device of claim 1 , wherein the energy barrier has a higher doping concentration than the channel region.
3. The semiconductor device of claim 1 , wherein the energy barrier comprises a first energy barrier.
4. The semiconductor device of claim 1 , wherein the energy barrier is formed from a hetero-barrier material.
5. The semiconductor device of claim 1 , wherein the gate stack comprises a floating gate to store a charge.
6. A semiconductor device comprising:
a semiconductor fin formed on a substrate, the semiconductor fin comprising an energy barrier between a source terminal and a channel region of the semiconductor fin;
a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of the channel region;
a conductive gate over the channel region of the semiconductor fin; and
a bottom spacer between the conductive gate and the substrate,
wherein the energy barrier and the channel region are doped using a first dopant, and wherein the source terminal and the drain terminal are doped using a second dopant.
7. The semiconductor device of claim 6 further comprising an active contact connecting the drain terminal of the semiconductor fin to a first line.
8. The semiconductor device of claim 7 , further comprising a gate contact connecting the conductive gate to a second line.
9. The semiconductor device of claim 6 , wherein the energy barrier is formed from a hetero-barrier material.
10. The semiconductor device of claim 6 , wherein the conductive gate comprises a floating gate.