IP Library Granted Patent US 10,903,238
Granted Patent B2
US 10,903,238 · App. 16/750,237 · Granted Jan 26, 2021

Semiconductor device and manufacturing method thereof

Inventors: Katsumi Yamamoto (Yokkaichi Mie, JP); Keisuke Kikutani (Yokkaichi Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11582H01L21/31144H01L21/76232H01L29/0649
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,903,238
App. No.
16/750,237
Granted
Jan 26, 2021
Kind
B2
Abstract

A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.

Claims (19)

1. A method of manufacturing a semiconductor device, comprising:

forming an insulator dividing a stacked body in which a plurality of layers are stacked in a first direction,

forming a first film on the stacked body, the first film having a first opening so that a part of the stacked body and the insulator are exposed from the first film,

forming a second film on the first film, the second film having a second opening with an opening dimension that is larger than a dimension of the first opening in a second direction and is smaller than a dimension of the first opening in a third direction such that the first opening and the second opening at least partially overlap with each other, wherein both the second direction and the third direction are perpendicular to the first direction; and

etching the stacked body and the insulator in the first direction using the second film as a mask.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein the second film has an etching rate ratio for etching the stacked body lower than an etching rate ratio of the first film.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein the second opening includes a circular shape.

4. The method of manufacturing a semiconductor device according to claim 1 , further comprising:

forming a first hole by the etching; and

forming memory cell films in the first hole, wherein the memory cell films including a first insulating layer, a second insulating layer, a third insulating layer and a semiconductor layer.

5. The method of manufacturing a semiconductor device according to claim 4 ,

wherein the plurality of layers include two kinds of insulating layers having different materials, stacked alternately,

the method further comprising:

forming a second hole having an opening diameter larger than an opening diameter of the insulator in another part of the insulator facing each other across the first hole using the first film after the formation of the first hole;

replacing one of the two kinds of insulating layers with a conductive layer using the second hole; and

burying an insulating material in the second hole.

6. The method of manufacturing a semiconductor device according to claim 5 , wherein

the second hole is formed by arranging a third film having a third opening on the first film at a position different from the formation position of the first hole, and

the third film has an etching rate ratio for etching the stacked body lower than an etching rate ratio of the first film.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
Priority Claims (1)
JP 2018-053207 · Mar 20, 2018 · national
Continuity (2)
Division 16105892 · Aug 20, 2018
Related Publication 20200161331A1 · May 21, 2020