IP Library › Granted Patent US 11,574,945
Granted Patent B2
US 11,574,945 · App. 16/763,024 · Granted Feb 7, 2023

Imaging device and electronic device

Inventors: Tatsuya Onuki (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP); Takanori Matsuzaki (Kanagawa, JP); Hajime Kimura (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/14634H01L27/1052H01L27/1207H01L27/1225H01L27/1255H01L29/7869H01L29/78648H04N5/37452H04N5/37455
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Quick Facts
Patent No.
US 11,574,945
App. No.
16/763,024
Granted
Feb 7, 2023
Kind
B2
Abstract

An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

Claims (40)

1. An imaging device comprising:

a first layer;

a second layer above the first layer; and

a third layer above the second layer,

wherein the first layer comprises a signal processing circuit,

wherein the second layer comprises a memory device,

wherein the third layer comprises an image sensor,

wherein the signal processing circuit comprises a first transistor formed on a first semiconductor substrate,

wherein the memory device comprises a second transistor comprising a metal oxide in a channel formation region,

wherein the image sensor comprises a plurality of pixels each comprising a third transistor and a photodiode,

wherein a semiconductor region of the third transistor comprises a first region of a second semiconductor substrate, and

wherein a semiconductor region of the photodiode comprises a second region of the second semiconductor substrate.

2. The imaging device according to claim 1 ,

wherein the signal processing circuit is configured to control operation of the memory device and the image sensor.

3. The imaging device according to claim 1 ,

wherein at least one of the signal processing circuit and the image sensor comprises an analog-digital conversion circuit, and

wherein the analog-digital conversion circuit is configured to convert image data generated by the image sensor to a digital signal.

4. The imaging device according to claim 3 ,

wherein the memory device is configured to retain the digital signal.

5. An imaging device comprising:

a first layer;

a second layer above the first layer; and

a third layer above the second layer,

wherein the first layer comprises a signal processing circuit,

wherein the second layer comprises a memory device,

wherein the third layer comprises an image sensor,

wherein the signal processing circuit comprises a first transistor formed on a first semiconductor substrate,

wherein the memory device comprises a plurality of memory cells,

wherein each of the plurality of the memory cells comprises a second transistor and a capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to a first electrode of the capacitor,

wherein the second transistor comprises a metal oxide in a channel formation region,

wherein the image sensor comprises a plurality of pixels each comprising a third transistor and a photodiode formed on a second semiconductor substrate, and

wherein the third transistor is stacked over the second transistor and the capacitor.

6. The imaging device according to claim 5 ,

wherein the signal processing circuit is configured to control operation of the memory device and the image sensor.

7. The imaging device according to claim 5 ,

wherein at least one of the signal processing circuit and the image sensor comprises an analog-digital conversion circuit, and

wherein the analog-digital conversion circuit is configured to convert image data generated by the image sensor to a digital signal.

8. The imaging device according to claim 7 ,

wherein the memory device is configured to retain the digital signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: ONUKI, TATSUYA; KATO, KIYOSHI; MATSUZAKI, TAKANORI; KIMURA, HAJIME; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 052624/0883 →
Priority Claims (2)
JP JP2017-225285 · Nov 23, 2017 · national
JP JP2018-030881 · Feb 23, 2018 · national
Continuity (1)
Related Publication 20200303444A1 · Sep 24, 2020
Cited By (3)
US 12,199,122 US 12,342,620 US 12,477,837